Abstract: A semiconductor memory has a first-stage amplifier circuit, wherein data stored in a memory cells is read based on a potential between an amplifier input MOS transistor and an amplifier reference MOS transistor, the potential being outputted from the first-stage amplifier circuit.

Abstract: A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit which exercises control to write the write object data into the non-volatile memory cells in accordance with the address output from the address search circuit.

Abstract: A semiconductor memory capable of storing and reading data in a memory cell for holding the data corresponding to a threshold voltage has a reference current generating circuit having a reference current generating section and an amplifier section.

Abstract: A method for controlling a threshold value in a nonvolatile semiconductor memory device, includes: performing writing at least once on at least one of the memory cells to be adjusted to a state other than an erased state with an applied voltage that does not cause excess writing, with verify reading being not performed; and performing verify reading by applying a verify voltage corresponding to a target threshold value of the memory cell after the writing is performed on the at least one of the memory cells to be adjusted to the state other than the erased state, and, when the threshold value of the memory cell is determined to be lower than the target threshold value, repeating the writing with the applied voltage that does not cause excess writing and the verify reading until the threshold value of the memory cell becomes equal to or higher than the target threshold value.

Abstract: A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell.

Abstract: A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.

Abstract: A reference current generating circuit has a plurality of current mirror circuits each having a mirror ratio different from another one, and generates a plurality of reference currents based on a current that flows to the reference memory cells. A plurality of sense amplifiers detects a current that flows to a selected memory cell based on the reference currents generated by the reference current generating circuit.

Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

Abstract: A reference current generating circuit has a plurality of current mirror circuits each having a mirror ratio different from another one, and generates a plurality of reference currents based on a current that flows to the reference memory cells. A plurality of sense amplifiers detects a current that flows to a selected memory cell based on the reference currents generated by the reference current generating circuit.

Abstract: A multi-chip package includes a first semiconductor memory controlled by a clock signal and an inverted clock signal, and a second semiconductor memory controlled by the clock signal. The first semiconductor memory and the second semiconductor memory each include a circuit for guaranteeing that a signal delay is suppressed between a peripheral circuit, and a pad to which the clock signal is input, a pad to which the inverted clock signal is input, a pad for outputting a data enable signal and a pad for outputting a data signal. Thus, it is guaranteed that the signal delay is suppressed, and the reliability of the multi-chip package is improved.

Abstract: A semiconductor device which continuously outputs data in synchronism with a first clock includes a clock generator which generates a second clock from the first clock which is externally supplied, a flip-flop circuit which operates in synchronism with the second clock, and receives the data, an output buffer circuit which outputs the output data from the flip-flop circuit outside, and a power supply circuit which includes a bandgap reference circuit, generates a voltage controlled by the bandgap reference circuit, and supplies the voltage as a power supply voltage to the clock generator, the flip-flop circuit, and the output buffer circuit.

Abstract: A reference current generating circuit has a plurality of current mirror circuits each having a mirror ratio different from another one, and generates a plurality of reference currents based on a current that flows to the reference memory cells. A plurality of sense amplifiers detects a current that flows to a selected memory cell based on the reference currents generated by the reference current generating circuit.

Abstract: A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supply potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.

Abstract: A semiconductor device comprises a board, a first semiconductor storage device placed on the board, and a second semiconductor storage device placed on the board. Each of the first and second semiconductor storage devices has a first pad for inputting a chip enable signal, a second pad for inputting a write enable signal, a third pad for inputting an output enable signal, a fourth pad for inputting an address signal, and a fifth pad for inputting data. The first semiconductor storage device has a sixth pad which is electrically connected to the first pad of the second semiconductor device, and the second semiconductor storage device has a seventh pad which is electrically connected to the first pad of the first semiconductor device.

Abstract: A sense amplifier has first and second input nodes. A reference memory cell is connected to the first input node. To the second input node, a constant current source circuit and a main memory cell are connected via a first transistor and a second transistor, respectively. A current mirror type load circuit is provided as a load circuit of the reference memory cell and the main memory cell. When a threshold voltage of the reference memory cell is adjusted, the first transistor is turned on and the second transistor is turned off. When the threshold voltage of the memory cell is adjusted at verification of writing to/erasing from the memory cell, the first transistor is turned off and the second transistor is turned on.

Abstract: A voltage generating circuit supplies first gate voltage to the control gate of a memory cell for a first control time period and supplies write voltage to the drain for a first write time period which is shorter than the first control time period when an operation of writing data into the memory cell is started. As the verify result, if it is detected that a data amount written into the memory cell is insufficient, the voltage generating circuit supplies second control voltage obtained by raising the first control gate voltage by constant voltage to the control gate for a time period which is shorter than the first control time period and supplies write voltage to the drain for a second write time period which is shorter than the first write time period.

Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

Abstract: A reference current generating circuit has a plurality of current mirror circuits each having a mirror ratio different from another one, and generates a plurality of reference currents based on a current that flows to the reference memory cells. A plurality of sense amplifiers detects a current that flows to a selected memory cell based on the reference currents generated by the reference current generating circuit.