Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

Abstract: A multi-chip package includes a first semiconductor memory controlled by a clock signal and an inverted clock signal, and a second semiconductor memory controlled by the clock signal. The first semiconductor memory and the second semiconductor memory each include a circuit for guaranteeing that a signal delay is suppressed between a peripheral circuit, and a pad to which the clock signal is input, a pad to which the inverted clock signal is input, a pad for outputting a data enable signal and a pad for outputting a data signal. Thus, it is guaranteed that the signal delay is suppressed, and the reliability of the multi-chip package is improved.

Abstract: A sense amplifier has first and second input nodes. A reference memory cell is connected to the first input node. To the second input node, a constant current source circuit and a main memory cell are connected via a first transistor and a second transistor, respectively. A current mirror type load circuit is provided as a load circuit of the reference memory cell and the main memory cell. When a threshold voltage of the reference memory cell is adjusted, the first transistor is turned on and the second transistor is turned off. When the threshold voltage of the memory cell is adjusted at verification of writing to/erasing from the memory cell, the first transistor is turned off and the second transistor is turned on.

Abstract: A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supple potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.

Abstract: A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

Abstract: A reference current generating circuit has a plurality of current mirror circuits each having a mirror ratio different from another one, and generates a plurality of reference currents based on a current that flows to the reference memory cells. A plurality of sense amplifiers detects a current that flows to a selected memory cell based on the reference currents generated by the reference current generating circuit.

Abstract: A voltage generating circuit supplies first gate voltage to the control gate of a memory cell for a first control time period and supplies write voltage to the drain for a first write time period which is shorter than the first control time period when an operation of writing data into the memory cell is started. As the verify result, if it is detected that a data amount written into the memory cell is insufficient, the voltage generating circuit supplies second control voltage obtained by raising the first control gate voltage by constant voltage to the control gate for a time period which is shorter than the first control time period and supplies write voltage to the drain for a second write time period which is shorter than the first write time period.

Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

Abstract: A semiconductor storage apparatus includes a cell array including memory cells and reference cells, normal column selection transistors connected to columns of the memory cells, a normal data line array including normal data lines connected to columns of the memory cells, first dummy data lines formed of a same wiring layer of which the normal data lines are formed, a normal data line charging circuit, reference column selection transistors connected to reference columns of the reference cells, a reference data line array including reference data lines formed of a same wiring layer of which the normal data lines are formed, second dummy data lines formed of a same wiring layer of which the reference data lines are formed, a reference data line charging circuit, a first dummy data line charging circuit, a second dummy data line charging circuit, and a sense amplifier which senses data stored in the memory cells.

Abstract: A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

Abstract: A semiconductor storage apparatus comprises a cell array including memory cells and reference cells, normal column selection transistors connected to columns of the memory cells, a normal data line array including normal data lines connected to columns of the memory cells, first dummy data lines formed of a same wiring layer of which the normal data lines are formed, a normal data line charging circuit, reference column selection transistors connected to reference columns of the reference cells, a reference data line array including reference data lines formed of a same wiring layer of which the normal data lines are formed, second dummy data lines formed of a same wiring layer of which the reference data lines are formed, a reference data line charging circuit, a first dummy data line charging circuit, a second dummy data line charging circuit, and a sense amplifier which senses data stored in the memory cells.

Abstract: A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

Abstract: A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank 0 or bank 1 and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.

Abstract: Several sense amplifiers detect data read from a memory cell of a bank in accordance with read address. Several first holding circuits individually hold data output from the sense amplifiers. Several second holding circuits hold data output from the corresponding first holding circuit after being delayed by time that the read address gains with respect to the burst address. Decoders individually supply data held in several second holding circuits to the corresponding line of a bus line.

Abstract: Several sense amplifiers detect data read from a memory cell of a bank in accordance with read address. Several first holding circuits individually hold data output from the sense amplifiers. Several second holding circuits hold data output from the corresponding first holding circuit after being delayed by time that the read address gains with respect to the burst address. Decoders individually supply data held in several second holding circuits to the corresponding line of a bus line.

Abstract: A nonvolatile semiconductor memory device with a plurality of read modes switchably built therein is provided. This nonvolatile semiconductor memory device is the one that has a memory cell array in which electrically rewritable nonvolatile memory cells are laid out and a read circuit which performs data readout of the memory cell array. The nonvolatile semiconductor memory device has a first read mode and a second read mode. The first read mode is for reading data by means of parallel data transfer of the same bit number when sending data from the memory cell array through the read circuit up to more than one external terminal. The second read mode is for performing parallel data transfer of a greater bit number than that of the first read mode when sending data from the memory cell array to the read circuit while performing data transfer of a smaller bit number than the bit number when sending data from the read circuit up to the external terminal.

Abstract: A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.

Abstract: A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

Abstract: A semiconductor memory device comprises a plurality of sense amplifiers divided into a plurality of groups, each of the groups being a unit of a page readout operation; a sense amplifier control signal generation circuit which outputs a sense amplifier control signal for enabling the sense amplifiers of each group and disabling the sense amplifiers of each group, wherein the sense amplifier control signal enables and disables the sense amplifiers of a part of the groups at different timing from the sense amplifiers of other groups; and a plurality of memory cells connected to the sense amplifiers via data lines.

Abstract: A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank 0 or bank 1 and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.