Abstract: A printed wiring board includes a first insulating layer having concave portions on first surface of the first insulating layer, a first conductor layer including first circuits formed in the concave portions, a second conductor layer including second circuits on second surface of the first insulating layer, a first via conductor connecting the first and second conductor layers, and a second insulating layer formed on the second surface of the first insulating layer and covering the second conductor layer. Each first circuit has upper, lower and side surfaces such that the upper surface is exposed from the first insulating layer and the side and lower surfaces are not roughened surfaces, each second circuit has top, back and side surfaces such that the side and back surfaces are roughened surfaces, and a thinnest first circuit has a line width L1 smaller than a line width L2 of a thinnest second circuit.

Abstract: A printed wiring board includes a first insulating layer, a first conductor layer formed on first surface of the first insulating layer, a second conductor layer formed on second surface of the first insulating layer, a first via structure formed in the first insulating layer such that the first via structure is connecting the first and second conductor layers, a second insulating layer formed on the second surface of the first insulating layer such that the second conductor layer is embedded into the second insulating layer, a third conductor layer formed on the second insulating layer, and a second via structure formed in the second insulating layer such that the second via structure is connecting the second and third conductor layers. The second conductor layer includes a dedicated wiring layer which transmits data between two electronic components to be mounted to the first surface of the first insulating layer.

Abstract: A package substrate includes resin insulating interlayers, and four or more conductive layers including dedicated wiring layers such that the dedicated wiring layers are two dedicated wiring layers which transmit data between a first electronic component and a second electronic component connected by the two dedicated wiring layers.

Abstract: A printed wiring board includes a resin insulation layer, a conductive layer formed on a surface of the resin insulation layer and including NSMD pads, and a solder-resist layer formed on the resin insulation layer and having openings such that the openings are exposing the NSMD pads, respectively. The solder-resist layer includes a lower solder-resist layer formed on the surface of the resin insulation layer and an upper solder-resist layer formed on the lower solder-resist layer, and each of the openings has a lower opening portion formed in the lower solder-resist layer and an upper opening portion formed in the upper solder-resist layer such that the upper opening portion has a size which is greater than a size of the lower opening portion.

Abstract: A package substrate includes an inner interlayer, a first conductor layer on the inner interlayer, a second conductor layer on which the inner interlayer is formed, an outermost interlayer on the first conductor layer, an outermost conductor layer on the outermost interlayer and including first and second pads positioned to mount first and second electronic components on the outermost interlayer, outermost vias connecting the first and outermost conductor layers through the outermost interlayer, and skip vias connecting the outermost and second conductor layers through the outermost and inner interlayers. The first conductor layer includes a first circuit connecting two outermost vias, and the outermost conductor layer includes an outermost circuit connecting one of the two outermost vias and one skip via such that the first conductor circuit, two outermost vias, outermost circuit and one skip via form a connection path connecting one second pad and the second conductor layer.

Abstract: A package substrate includes an outermost interlayer, an outermost conductive layer including first pads positioned to mount at electronic component and second pads positioned to mount another electronic component, a first conductive layer including first circuits and formed such that the outermost interlayer is on the first conductive layer and that the first circuits are connecting the first and second pads, an inner interlayer formed such that the first conductive layer is on the inner interlayer, a second conductive layer formed such that the inner interlayer is on the second conductive layer, via conductors penetrating through the outermost interlayer and including first via conductors connecting the first conductive layer and the first pads and second via conductors connecting the first conductive layer and the second pads, and third via conductors penetrating through the inner interlayer and positioned such that the first and third via conductors form stacked via conductors.

Abstract: A package substrate includes a core substrate, a first buildup layer and a second buildup layer. The first buildup layer includes an uppermost interlayer, an upper inner interlayer, an uppermost conductive layer including first pads and second pads, an upper first conductive layer, an upper second conductive layer, vias formed through the uppermost interlayer and connecting the upper first conductive layer and the second pads, and skip vias formed through the uppermost and upper inner interlayers and connecting the uppermost and upper second conductive layers. The second buildup layer includes a lowermost interlayer, a lower inner interlayer, a lowermost conductive layer including third pads, a lower first conductive layer, a lower second conductive layer, vias formed through the lowermost interlayer and connecting the lower first conductive layer and third pads, and skip vias formed through the lowermost and lower inner interlayers and connecting the lowermost and lower second conductive layers.

Abstract: A printed wiring board includes a wiring conductor layer having a first surface, conductor posts formed on a second surface of the wiring conductor layer on the opposite side with respect to the first surface, and a resin insulating layer embedding the wiring conductor layer such that the first surface of the wiring conductor layer is recessed with respect to a first surface of the resin insulating layer and exposed on the first surface of the resin insulating layer and covering side surfaces of the conductor posts such that an end surface of each of the conductor posts is protruding from a second surface of the resin insulating layer on the opposite side with respect to the first surface of the resin insulating layer.

Abstract: A printed wiring board includes an insulating layer, a first conductor layer embedded into a first surface of the insulating layer and including connecting portions to connect an electronic component, a second conductor layer projecting from a second surface of the insulating layer, a solder resist layer covering the first conductor layer and having an opening structure exposing the connecting portions, a barrier metal layer formed on the connecting portions such that the barrier layer is projecting from the first surface of the insulating layer, and metal posts formed on the barrier layer such that the metal posts are positioned on the connecting portions, respectively. Each metal post has width which is greater than width of a respective connecting portion, and the barrier metal layer includes a metal material which is different from a metal material forming the metal posts and a metal material forming the first conductor layer.

Abstract: A printed wiring board includes a wiring conductor layer having first surface, conductor posts formed on second surface of the wiring layer, and an insulating layer embedding the wiring layer such that the first surface of the wiring layer is exposed on first surface of the insulating layer and covering side surfaces of the posts such that end surface of each conductor post is exposed from second surface of the insulating layer. The first surface of the wiring layer is recessed with respect to the first surface of the insulating layer and the end surface of each conductor post is recessed with respect to the second surface of the insulating layer such that distance between the end surface of each conductor post and the second surface of the insulating layer is greater than distance between the first surface of the wiring layer and the first surface of the insulating layer.

Abstract: A printed wiring board includes an insulating layer, a first conductor layer embedded into first surface of the insulating layer and including multiple wirings such that the wirings include connecting portions positioned to connect an electronic component, respectively, a second conductor layer projecting from second surface of the insulating layer on the opposite side, a solder resist layer formed on the first surface of the insulating layer such that the solder resist layer is covering the first conductor layer and has an opening structure exposing the connecting portions of the wirings, and multiple metal posts formed on the connecting portions respectively such that each of the metal posts has a width which is larger than a width of a respective one of the wirings having the connecting portions. The wirings are formed such that the connecting portions are positioned side by side on every other adjacent one of the wirings.

Abstract: A printed wiring board includes a insulation layer, a first conductive layer embedded into first surface of the insulation layer and having surface exposed on the first surface of the insulation layer, a second conductive layer formed on second surface of the insulation layer and protruding from the second surface of the insulation layer, a via penetrating through the insulation layer and electrically connecting the first and second conductive layers, a solder-resist layer covering the first conductive layer and having an opening structure forming an exposed structure of the first conductive layer, and a metal layer formed on the exposed structure and protruding from the first surface of the insulation layer. The exposed structure of the first conductive layer includes pads positioned to mount an electronic component to the first conductive layer, and the metal layer has a solder layer formed on the metal layer and having a flat surface.

Abstract: A printed wiring board includes an insulation layer, a first conductive layer embedded into first surface of the insulation layer, a second conductive layer formed on second surface of the insulation layer, a via conductor penetrating through the insulation layer and electrically connecting the first and second layers, and a solder-resist layer covering the first layer and having an opening structure forming an exposed structure of the first layer. The exposed structure is formed to connect an electronic component to the first layer, and the first layer has a barrier-metal layer and a metal layer on the first layer such that the barrier-metal layer is on surface of the first layer and includes metal different from metal forming the metal layer and that the metal layer is on surface of the barrier-metal layer in the exposed structure and protruding from the first surface of the insulation layer.

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 ?m and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 ?m. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

Abstract: A package substrate includes an inner interlayer, a first conductor layer on the inner interlayer, a second conductor layer on which the inner interlayer is formed, an outermost interlayer on the first conductor layer, an outermost conductor layer on the outermost interlayer and including first and second pads positioned to mount first and second electronic components on the outermost interlayer, outermost vias connecting the first and outermost conductor layers through the outermost interlayer, and skip vias connecting the outermost and second conductor layers through the outermost and inner interlayers. The first conductor layer includes a first circuit connecting two outermost vias, and the outermost conductor layer includes an outermost circuit connecting one of the two outermost vias and one skip via such that the first conductor circuit, two outermost vias, outermost circuit and one skip via form a connection path connecting one second pad and the second conductor layer.

Abstract: A package substrate includes an inner interlayer, a first conductor layer, a second conductor layer, an outermost interlayer, an outermost conductor layer including first and second pads to mount electronic components, vias including first and second vias such that the first vias are connecting the first conductor layer and first pads and the second vias are connecting the first conductor layer and second pads, and skip vias penetrating through the outermost and inner interlayers such that the skip vias are connecting the outermost and second conductor layers. Sum of insulation distances (t1, t2) is in range of 40 ?m or less to 10 ?m or more, where the insulation distance (t1) is insulation distance between the outermost and first conductor layers and the insulation distance (t2) is insulation distance between the first and second conductor layers, and difference between the insulation distances (t1, t2) is less than 5 ?m.

Abstract: A package substrate includes a core substrate, a first buildup layer and a second buildup layer. The first buildup layer includes an uppermost interlayer, an upper inner interlayer, an uppermost conductive layer including first pads and second pads, an upper first conductive layer, an upper second conductive layer, vias formed through the uppermost interlayer and connecting the upper first conductive layer and the second pads, and skip vias formed through the uppermost and upper inner interlayers and connecting the uppermost and upper second conductive layers. The second buildup layer includes a lowermost interlayer, a lower inner interlayer, a lowermost conductive layer including third pads, a lower first conductive layer, a lower second conductive layer, vias formed through the lowermost interlayer and connecting the lower first conductive layer and third pads, and skip vias formed through the lowermost and lower inner interlayers and connecting the lowermost and lower second conductive layers.

Abstract: A package substrate includes interlayer insulating layers including outermost and inner-layer layers, conductor layers including an outermost layer, a first layer between the outermost and inner-layer layers, and a second layer on which the inner-layer layer is formed, via conductors including first and second conductors through the outermost insulating layer, and skip via conductors through the outermost and inner-layer insulating layers to connect the outermost and second conductor layers. The outermost conductor layer includes first and second pads to mount first and second electronic components on the outermost insulating layer, the first conductors are positioned to connect the first conductor layer and first pads, the second conductors are positioned to connect the first conductor layer and second pads, and the first conductor layer has area on surface of the inner-layer insulating layer which is in range of 3 to 15% of area of the surface of the inner-layer insulating layer.

Abstract: A printed circuit board includes a substrate having an opening portion, a chip capacitor device accommodated in the opening portion of the substrate, and a buildup structure formed on the substrate such that the buildup structure covers the chip capacitor device in the opening portion of the substrate. The chip capacitor has a dielectric body having a surface facing the buildup structure, first electrodes formed on the surface of the dielectric body and second electrodes formed on the surface of the dielectric body, and the buildup structure has first via structures and second via structures such that the first via structures are connected to the first electrodes, respectively, and the second via structures are connected to the second electrodes, respectively.

Abstract: A multilayer printed wiring board includes a core substrate having a through-hole formed through the substrate, an interlayer insulation layer formed on the substrate and having a via conductor formed through the insulation layer, and a conductor layer formed on the insulation layer and connected to the via in the insulation layer. The substrate has multiplayer insulation structure, outer power layer formed on surface of the structure, outer ground layer formed on opposite surface of the structure, inner power layer formed inside the structure and inner ground layer formed inside the structure, each of the inner layers has tapered end having angle satisfying 2.8<tan ?<55, the through-hole is penetrating through and insulated from the inner layers, and the inner layers are positioned between the outer layers such that the inner power layer is between the ground layers and the inner ground layer is between the power layers.