Patents by Inventor Yasushi Inagaki

Yasushi Inagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150212288
    Abstract: A lens driving apparatus includes a lens holding member, a static member including a housing, a biasing member, and a moving mechanism. The biasing member includes upper and lower leaf springs. The upper leaf spring includes an upper first portion, an upper second portion, and an upper elastic arm portion. A through hole is formed in the upper first portion of the upper leaf spring. The lens holding member includes a fastening portion that includes a mount surface on which the upper leaf spring is placed, a recess facing the through hole, and a protrusion inserted into the through hole. An adhesive held in the recess surrounds the protrusion and part of the adhesive spreads to an upper surface of the upper first portion of the upper leaf spring through the through hole. The upper leaf spring is fixed to the lens holding member with the adhesive.
    Type: Application
    Filed: January 26, 2015
    Publication date: July 30, 2015
    Inventors: Yasushi INAGAKI, Katsuhiko OTOMO
  • Patent number: 9060446
    Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: June 16, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Publication number: 20150043183
    Abstract: A wiring board with a built-in electronic component includes a core substrate, an electronic component in the substrate, a first upper-layer structure on first surface of the substrate, a second upper-layer structure on second surface of the substrate, and via conductors in the substrate and first upper-layer structure such that the via conductors are connected to an electrode of the component. The substrate has an accommodating layer, a first connection layer on first surface of the accommodating layer, and a second connection layer on second surface of the accommodating layer, the accommodating layer includes inner wiring and insulation layers and has cavity accommodating the component, the first connection layer includes inner wiring and insulation layers, and the second connection layer includes inner wiring and insulation layers such that the second connection layer includes greater number of inner wiring and insulation layers than the first connection layer.
    Type: Application
    Filed: August 8, 2014
    Publication date: February 12, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Naohito ISHIGURO, Yasushi Inagaki
  • Publication number: 20150040389
    Abstract: A method for manufacturing a wiring board with a built-in electronic component includes positioning an electronic component in a cavity of a substrate, forming intermediate structures each including an intermediate insulation layer and an intermediate wiring-pattern layer on upper and lower surfaces of the substrate, respectively, such that a component-accommodating substrate is formed, attaching a support sheet to a first surface of the component-accommodating substrate, forming a connection layer including insulation layers and wiring-pattern layers on a second surface of the component-accommodating substrate on the opposite side with respect to the first surface of the component-accommodating substrate, removing the support sheet from the component-accommodating substrate such that an intermediate laminate structure having the connection layer laminated on the second surface of the component-accommodating substrate is formed, and forming upper-layer structures each including an insulation layer and a wirin
    Type: Application
    Filed: August 8, 2014
    Publication date: February 12, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Naohito ISHIGURO, Yasushi INAGAKI
  • Publication number: 20140374150
    Abstract: A package substrate includes an outermost interlayer resin insulation layer, an outermost conductive layer formed on a first surface of the outermost interlayer resin insulation layer and including first pads positioned to mount a first electronic component and second pads positioned to mount a second electronic component, a first conductive layer including first conductive circuits and formed on a second surface of the outermost interlayer resin insulation layer on the opposite side with respect to the first surface, first via conductors penetrating through the outermost interlayer resin insulation layer such that the first via conductors are connecting the first conductive layer and the first pads, and second via conductors penetrating through the outermost interlayer resin insulation layer such that the second via conductors are connecting the first conductive layer and the second pads. The first conductive circuits in the first conductive layer are connecting the first and second pads, respectively.
    Type: Application
    Filed: June 20, 2014
    Publication date: December 25, 2014
    Applicant: IBIDEN CO., LTD.
    Inventors: Yasushi INAGAKI, Yasuhiro Takahashi, Satoshi Kurokawa
  • Patent number: 8842440
    Abstract: A method for manufacturing a printed circuit board includes forming an opening portion in a substrate, positioning chip capacitors in the opening portion of the substrate such that the chip capacitors are accommodated in the opening portion of the substrate, forming a buildup structure including an interlayer resin insulating layer and a conductive layer over a surface of the substrate and the chip capacitors accommodated in the opening portion of the substrate, and forming on a surface of the buildup structure bump structures positioned to mount an IC chip such that the chip capacitors in the opening portion of the substrate are positioned directly below the IC chip.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 23, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 8830691
    Abstract: A printed circuit board including a core substrate including a first resin substrate, a second resin substrate having an opening and a third resin substrate in a multilayer manner while interposing bonding plates, insulating layers and conductive circuit layers alternately laminated on the core substrate, solder bumps formed on an outer surface of the printed circuit board, a first capacitor formed in the opening of the second resin substrate, a conductive pad formed on the first resin substrate and connected to an electrode of the first capacitor, a via hole formed in the first resin substrate and directly connected to the conductive pad and a conductive circuit on the core substrate, and a second capacitor mounted on a surface of the printed circuit board.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: September 9, 2014
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Publication number: 20140247572
    Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 4, 2014
    Applicant: IBIDEN CO., LTD.
    Inventors: Yasushi INAGAKI, Motoo ASAI, Dongdong WANG, Hideo YABASHI, Seiji SHIRAI
  • Patent number: 8780573
    Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 15, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi
  • Patent number: 8763241
    Abstract: A method for manufacturing a printed circuit board including providing a first resin substrate having a resin plate and a circuit pattern formed on a surface of the resin plate, providing a second resin substrate having a resin plate and an accommodation portion formed in the resin plate of the second substrate, connecting an electrode of a capacitor to the circuit pattern of the first substrate with a bonding material such that the capacitor is mounted to the first substrate, attaching the second substrate to the resin substrate through a bonding resin layer such that the capacitor on the first substrate is accommodated in the accommodation portion of the second substrate, and forming a via hole in the first substrate such that the via hole is electrically connected to the electrode of the capacitor in the accommodation portion of the second substrate.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 1, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 8754334
    Abstract: An IC chip for a high frequency region, particularly a packaged substrate in which no malfunction or error occurs even if 3 GHz is exceeded. A conductive layer on a core substrate is formed at a thickness of 30 ?m and a conductor circuit on an interlayer resin insulation layer is formed at a thickness of 15 ?m. By thickening the conductive layer, the volume of the conductor can be increased and resistance can be reduced. Further, by using the conductive layer as a power source layer, the capacity of supply of power to an IC chip can be improved.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: June 17, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Katsuyuki Sano
  • Patent number: 8729400
    Abstract: An IC chip for a high frequency region, particularly a packaged substrate in which no malfunction or error occurs even if 3 GHz is exceeded. A conductive layer on a core substrate is formed at a thickness of 30 ?m and a conductor circuit on an interlayer resin insulation layer is formed at a thickness of 15 ?m. By thickening the conductive layer, the volume of the conductor can be increased and resistance can be reduced. Further, by using the conductive layer as a power source layer, the capacity of supply of power to an IC chip can be improved.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: May 20, 2014
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yasushi Inagaki, Katsuyuki Sano
  • Patent number: 8717772
    Abstract: A printed circuit board includes a core substrate having an opening portion, an electronic component provided in the opening portion of the core substrate and including a dielectric body, a first electrode formed over the dielectric body, and a second electrode formed over the dielectric body such that the dielectric body is interposed between the first electrode and the second electrode, and a resin filling a gap between the core substrate and the electronic component in the opening portion of the core substrate. The resin filling the gap includes a filler.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 6, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 8592688
    Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 ?m and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 ?m. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: November 26, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Katsuyuki Sano
  • Publication number: 20130299218
    Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 ?m and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 ?m. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.
    Type: Application
    Filed: July 8, 2013
    Publication date: November 14, 2013
    Inventors: Yasushi INAGAKI, Katsuyuki Sano
  • Publication number: 20130286615
    Abstract: A method for manufacturing a printed circuit board includes forming an opening portion in a substrate, positioning chip capacitors in the opening portion of the substrate such that the chip capacitors are accommodated in the opening portion of the substrate, forming a buildup structure including an interlayer resin insulating layer and a conductive layer over a surface of the substrate and the chip capacitors accommodated in the opening portion of the substrate, and forming on a surface of the buildup structure bump structures positioned to mount an IC chip such that the chip capacitors in the opening portion of the substrate are positioned directly below the IC chip.
    Type: Application
    Filed: June 28, 2013
    Publication date: October 31, 2013
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 8569880
    Abstract: A multilayer printed wiring board in which interlayer insulation layer and conductive layer are formed on a multilayer core substrate composed of three or more layers, having through holes for connecting the front surface with the rear surface and conductive layers on the front and rear surfaces and conductive layer in the inner layer to achieve electric connection through via holes, the through holes being composed of power source through holes, grounding through holes and signal through holes connected electrically to a power source circuit or a grounding circuit or a signal circuit of an IC chip, when the power source through holes pass through the grounding conductive layer of the inner layer in the core substrate, of the power source through holes, at least a power source through hole just below the IC having no conductive circuit extending from the power source through hole in the grounding conductive layer.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: October 29, 2013
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yasushi Inagaki, Katsuyuki Sano
  • Publication number: 20130248234
    Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 ?m and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 ?m. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.
    Type: Application
    Filed: April 29, 2013
    Publication date: September 26, 2013
    Applicant: IBIDEN CO., LTD.
    Inventors: Yasushi Inagaki, Katsuyuki Sano
  • Publication number: 20130107482
    Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 2, 2013
    Inventors: Yasushi INAGAKI, Motoo ASAI, Dongdong WANG, Hideo YABASHI, Seiji SHIRAI
  • Patent number: 8331102
    Abstract: Chip capacitors are provided in a printed circuit board. In this manner, the distance between the IC chip and each chip capacitor is shortened, and the loop inductance is reduced. In addition, the chip capacitors are accommodated in a core substrate having a large thickness. Therefore, the thickness of the printed circuit board does not become large.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: December 11, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai