Patents by Inventor Yasushi Shiraishi

Yasushi Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6911722
    Abstract: A semiconductor apparatus includes a semiconductor device to be mounted on a circuit board; a plurality of conductive posts electrically connected to the semiconductor device; and a plurality of conductive bumps each provided on an outer end of each of the conductive posts, so that the plurality of conductive bump is soldered onto the circuit board when the semiconductor device is mounted on the circuit board. A distance between a peripheral edge of the semiconductor device and an outer edge of the conductive post is determined to be narrow so that a solderbility or wetting condition of the conductive bumps can be visibly recognized easily.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: June 28, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Yasushi Shiraishi, Yasuo Tanaka
  • Patent number: 6852564
    Abstract: A semiconductor device is disclosed which includes a semiconductor chip having a plurality of electrode pads on its upper surface; terminals such as copper posts formed on the upper surface of the semiconductor chip, and electrically connected to each of the electrode pads; a resin deposited on the upper surface of the semiconductor chip, encapsulating the terminals but exposing at least some of them to a predetermined height; and electroconductor members such as solder balls connected to the terminals. There is also disclosed a method of fabricating such a semiconductor device.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: February 8, 2005
    Assignee: Oki Electric Industry Co, Ltd.
    Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
  • Publication number: 20040099937
    Abstract: A semiconductor device in accordance with the present invention reduces cracks occurring in a junction between a semiconductor device and a mounting substrate due to a heat stress when the semiconductor device is mounted on a printed circuit board or the like. The semiconductor device has a semiconductor element having a thickness of 200 &mgr;m or less, an electrode pad formed an the semiconductor element, a post electrically connected to the electrode pad, and a sealing resin for sealing a surface where circuitry is formed and the post.
    Type: Application
    Filed: November 24, 2003
    Publication date: May 27, 2004
    Inventors: Shinji Ohuchi, Yasushi Shiraishi
  • Publication number: 20040046256
    Abstract: The invention provides a semiconductor device and a method for manufacturing the same, enabling the semiconductor device to be high-densely packaged without lowering the final manufacturing yield of products.
    Type: Application
    Filed: September 9, 2003
    Publication date: March 11, 2004
    Inventors: Shinji Ohuchi, Shigeru Yamada, Yasushi Shiraishi
  • Patent number: 6680535
    Abstract: A semiconductor device in accordance with the present invention reduces cracks occurring in a junction between a semiconductor device and a mounting substrate due to a heat stress when the semiconductor device is mounted on a printed circuit board or the like. The semiconductor device has a semiconductor element having a thickness of 200 &mgr;m or less, an electrode pad formed on the semiconductor element, a post electrically connected to the electrode pad, and a sealing resin for sealing a surface where circuitry is formed and the post.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: January 20, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Yasushi Shiraishi
  • Patent number: 6673651
    Abstract: A method of manufacturing a semiconductor device includes mounting a first semiconductor element on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: January 6, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Shigeru Yamada, Yasushi Shiraishi
  • Patent number: 6653218
    Abstract: A polyimide layer is formed over a semiconductor chip, a rewiring to be connected to each of the electrode pads of the semiconductor chip is formed over the polyimide layer, and a post serving as a terminal is connected to each of the electrode pads via the rewiring, thereby redisposing the electrode pads. A resin for encapsulating the rewirings and the posts is formed on the surface of the semiconductor chip to the extent equivalent to the dimension of the semiconductor chip, and in a groove formed in portions of the resin, around the respective posts, the topmost surface and the sidewall face of the respective posts are exposed out of the resin.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: November 25, 2003
    Assignee: Oki Electric Industry Co, Ltd.
    Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
  • Patent number: 6630972
    Abstract: A transmission liquid crystal panel blocks rays of light incident on a multiplicity of thin film transistors from above not only with an upper metal film of high reflectance but also with at least one of light blocking film of low light transmittance. The light blocking film of low reflectance is laminated below the upper metal film and above the thin film transistors, and a light absorbing film of low reflectance is laminated above a multiplicity of lower light blocking films and below the thin film transistors. Thus, even if rays of light reflected by the lower surface of a transparent substrate is multiple reflected by the lower surface of the upper metal film or the upper surface of the lower light blocking film, stray light generated from the multiple reflections does not reach the thin film transistors. Therefore the stray light is prevented from impairing the operations of the thin film transistors.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: October 7, 2003
    Assignee: NEC Corporation
    Inventor: Yasushi Shiraishi
  • Publication number: 20030173658
    Abstract: A semiconductor device in accordance with the present invention reduces cracks occurring in a junction between a semiconductor device and a mounting substrate due to a heat stress when the semiconductor device is mounted on a printed circuit board or the like. The semiconductor device has a semiconductor element having a thickness of 200 &mgr;m or less, an electrode pad formed on the semiconductor element, a post electrically connected to the electrode pad, and a sealing resin for sealing a surface where circuitry is formed and the post.
    Type: Application
    Filed: March 13, 2003
    Publication date: September 18, 2003
    Inventors: Shinji Ohuchi, Yasushi Shiraishi
  • Patent number: 6613694
    Abstract: A semiconductor device in accordance with the present invention reduces cracks occurring in a junction between a semiconductor device and a mounting substrate due to a heat stress when the semiconductor device is mounted on a printed circuit board or the like. The semiconductor device has a semiconductor element having a thickness of 200 &mgr;m or less, an electrode pad formed on the semiconductor element, a post electrically connected to the electrode pad, and a sealing resin for sealing a surface where circuitry is formed and the post.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: September 2, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Yasushi Shiraishi
  • Publication number: 20030102545
    Abstract: A semiconductor device which is sealed with a plastic sealing layer and whose thickness is regulated to be below a given value is known. Since the thickness of the device is small, and the thickness of the upper portion of the plastic sealing layer and the thickness of the lower portion thereof are different from each other, the plastic sealing layer becomes warped, thus causing a crack on the side of the semiconductor chip.
    Type: Application
    Filed: January 14, 2003
    Publication date: June 5, 2003
    Inventors: Etsuo Yamada, Kenji Nagasaki, Yasushi Shiraishi, Kazuhiko Sera
  • Patent number: 6573598
    Abstract: A semiconductor device is disclosed which includes a semiconductor chip having a plurality of electrode pads on its upper surface; terminals such as copper posts formed on the upper surface of the semiconductor chip, and electrically connected to each of the electrode pads; a resin deposited on the upper surface of the semiconductor chip, encapsulating the terminals but exposing at least some of them to a predetermined height; and electroconductor members such as solder balls connected to the terminals. There is also disclosed a method of fabricating such a semiconductor device.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: June 3, 2003
    Assignee: Oki Electric Industry Co, Ltd.
    Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
  • Publication number: 20030092219
    Abstract: There is disclosed a semiconductor device, comprising: a semiconductor chip having a plurality of electrode pads on the upper surface; a terminal formed on the upper surface of the semiconductor chip, and electrically connected to each of the electrode pads; a resin formed on the upper surface of the semiconductor chip, encapsulating the terminal to be exposed to the extent of a predetermined height; and an electroconductor connected to the terminal. There is also disclosed a method of fabricating such a semiconductor device.
    Type: Application
    Filed: November 27, 2002
    Publication date: May 15, 2003
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
  • Publication number: 20030071352
    Abstract: A polyimide layer is formed over a semiconductor chip, a rewiring to be connected to each of the electrode pads of the semiconductor chip is formed over the polyimide layer, and a post serving as a terminal is connected to each of the electrode pads via the rewiring, thereby redisposing the electrode pads. A resin for encapsulating the rewirings and the posts is formed on the surface of the semiconductor chip to the extent equivalent to the dimension of the semiconductor chip, and in a groove formed in portions of the resin, around the respective posts, the topmost surface and the sidewall face of the respective posts are exposed out of the resin.
    Type: Application
    Filed: November 5, 2002
    Publication date: April 17, 2003
    Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
  • Patent number: 6534845
    Abstract: A semiconductor. device comprises a semiconductor chip on which a plurality of grooves are defined, thus acting as a resisting member, the effect of which is to prevent the semiconductor chip from bending. Consequently, the thickness of the lower portion of the plastic layer becomes greater, thereby preventing cracks from occurring on the semiconductor chip.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: March 18, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Etsuo Yamada, Kenji Nagasaki, Yasushi Shiraishi, Kazuhiko Sera
  • Publication number: 20030006510
    Abstract: A semiconductor device in accordance with the present invention reduces cracks occurring in a junction between a semiconductor device and a mounting substrate due to a heat stress when the semiconductor device is mounted on a printed circuit board or the like. The semiconductor device has a semiconductor element having a thickness of 200 &mgr;m or less, an electrode pad formed on the semiconductor element, a post electrically connected to the electrode pad, and a sealing resin for sealing a surface where circuitry is formed and the post.
    Type: Application
    Filed: September 6, 2002
    Publication date: January 9, 2003
    Inventors: Shinji Ohuchi, Yasushi Shiraishi
  • Patent number: 6495916
    Abstract: A polyimide layer is formed over a semiconductor chip, a rewiring to be connected to each of the electrode pads of the semiconductor chip is formed over the polyimide layer, and a post serving as a terminal is connected to each of the electrode pads via the rewiring, thereby redisposing the electrode pads. A resin for encapsulating the rewirings and the posts is formed on the surface of the semiconductor chip to the extent equivalent to the dimension of the semiconductor chip, and in a groove formed in portions of the resin, around the respective posts, the topmost surface and the sidewall face of the respective posts are exposed out of the resin.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: December 17, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
  • Publication number: 20020167085
    Abstract: There is disclosed a semiconductor device, comprising: a semiconductor chip having a plurality of electrode pads on the upper surface; a terminal formed on the upper surface of the semiconductor chip, and electrically connected to each of the electrode pads; a resin formed on the upper surface of the semiconductor chip, encapsulating the terminal to be exposed to the extent of a predetermined height; and an electroconductor connected to the terminal. There is also disclosed a method of fabricating such a semiconductor device.
    Type: Application
    Filed: April 4, 2000
    Publication date: November 14, 2002
    Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
  • Patent number: 6476501
    Abstract: A semiconductor device in accordance with the present invention reduces cracks occurring in a junction between a semiconductor device and a mounting substrate due to a heat stress when the semiconductor device is mounted on a printed circuit board or the like. The semiconductor device has a semiconductor element having a thickness of 200 &mgr;m or less, an electrode pad formed on the semiconductor element, a post electrically connected to the electrode pad, and a sealing resin for sealing a surface where circuitry is formed and the post.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: November 5, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Yasushi Shiraishi
  • Patent number: 6403398
    Abstract: A resin sealing type semiconductor device, a manufacturing method thereof and a packaging structure thereof are capable of downsizing the semiconductor device and attaining high-density packaging. For this, the resin sealing type semiconductor device with leads exposed in an outer surface, is provided with spot leads adhered to a circuit forming surface of a semiconductor element with an insulating adhesive tape interposed therebetween, each independently regularly arrayed, and exposed to outside with the semiconductor element disposed inside.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: June 11, 2002
    Assignee: Oki Electric Industry Co, Ltd.
    Inventors: Shinji Ohuchi, Yasushi Shiraishi, Hiroshi Kawano, Etsuo Yamada