Patents by Inventor Yasushi Shiraishi

Yasushi Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020060367
    Abstract: A semiconductor apparatus includes a semiconductor device to be mounted on a circuit board; a plurality of conductive posts electrically connected to the semiconductor device; and a plurality of conductive bumps each provided on an outer end of each of the conductive posts, so that the plurality of conductive bump is soldered onto the circuit board when the semiconductor device is mounted on the circuit board. A distance between a peripheral edge of the semiconductor device and an outer edge of the conductive post is determined to be narrow so that a solderbility or wetting condition of the conductive bumps can be visibly recognized easily.
    Type: Application
    Filed: April 27, 2001
    Publication date: May 23, 2002
    Inventors: Shinji Ohuchi, Yasushi Shiraishi, Yasuo Tanaka
  • Patent number: 6392262
    Abstract: An indium layer sandwiched between palladium layers are treated with heat so that the indium is diffused into a p-type gallium arsenide, and is alloyed with the palladium, whereby the p-type indium gallium arsenide layer decreases a Schottky barrier between the p-type gallium arsenide and the palladium-indium alloy layer.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: May 21, 2002
    Assignee: NEC Corporation
    Inventor: Yasushi Shiraishi
  • Publication number: 20020047199
    Abstract: A semiconductor device capable mounting semiconductor elements having different functions without increasing the area of the semiconductor device, and its manufacturing method are presented. A part of wiring 104 is formed al so at the side surface of a semiconductor element 101, and bump electrodes 102 formed so as to be nearly on a same plane as the wiring 104 formed at the side surface of the semiconductor element 101, at least a part of ball electrodes 103 is formed so as to connect electrically to the wiring 104 at the side surface of the semiconductor element, the side surface of the semiconductor element is sealed with resin exposing the wiring 104, and the confronting surface of the circuit forming surface is sealed with resin.
    Type: Application
    Filed: May 11, 2001
    Publication date: April 25, 2002
    Inventors: Shinji Ohuchi, Yasushi Shiraishi, Yasuo Tanaka
  • Patent number: 6262482
    Abstract: In a semiconductor device 1 according to the present invention, a plurality of inner leads are bonded to a front surface of a semiconductor element 11 covered by a package 10, with bent portions 17 formed at some inner leads 13a among the plurality of inner leads 13 and the front ends of the bent portions 17 exposed at a front surface of the package 10. This structure ensures that the semiconductor element is not caused to move vertically inside the forming die by the pressure of the liquid resin or the like during the sealing process.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: July 17, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yasushi Shiraishi, Kazuhiko Sera, Etsuo Yamada, Kenji Nagasaki
  • Patent number: 6258621
    Abstract: In a plastic packaged semiconductor device, a chip support formed on the same lead frame as leads is disposed so as to extend over the surface of a semiconductor element, the chip support is bonded and fixed to the surface of a polyimide wafer coat on the semiconductor element by means of an insulating tape, the leads are brought into contact with the polyimide wafer coat on the semiconductor element without being fixed, the leads and the electrodes of the semiconductor element are connected by means of gold wires, and these are packaged by a packaging material. Generation of crack in the sealing material thereby prevented, and the thickness of the plastic packaged semiconductor device is reduced.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: July 10, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Hiroshi Kawano, Etsuo Yamada, Yasushi Shiraishi
  • Publication number: 20010005600
    Abstract: The invention provides a semiconductor device and a method for manufacturing the same, enabling the semiconductor device to be high-densely packaged without lowering the final manufacturing yield of products.
    Type: Application
    Filed: January 11, 2001
    Publication date: June 28, 2001
    Inventors: Shinji Ohuchi, Shigeru Yamada, Yasushi Shiraishi
  • Publication number: 20010001217
    Abstract: A resin sealing type semiconductor device, a manufacturing method thereof and a packaging structure thereof are capable of downsizing the semiconductor device and attaining high-density packaging. For this, the resin sealing type semiconductor device with leads exposed in an outer surface, is provided with spot leads adhered to a circuit forming surface of a semiconductor element with an insulating adhesive tape interposed therebetween, each independently regularly arrayed, and exposed to outside with the semiconductor element disposed inside.
    Type: Application
    Filed: December 12, 2000
    Publication date: May 17, 2001
    Inventors: Shinji Ohuchi, Yasushi Shiraishi, Hiroshi Kawano, Etsuo Yamada
  • Patent number: 6208021
    Abstract: A resin sealing type semiconductor device, a manufacturing method thereof and a packaging structure thereof are capable of downsizing the semiconductor device and attaining high-density packaging. For this, the resin sealing type semiconductor device with leads exposed in an outer surface, is provided with spot leads adhered to a circuit forming surface of a semiconductor element with an insulating adhesive tape interposed therebetween, each independently regularly arrayed, and exposed to outside with the semiconductor element disposed inside.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: March 27, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Yasushi Shiraishi, Hiroshi Kawano, Etsuo Yamada
  • Patent number: 6201266
    Abstract: A densely packaged semiconductor device includes a first semiconductor device having a plurality of bumps which are formed on a backside surface thereof, and a second semiconductor device having a plurality of terminals which are formed on the front surface thereof and which are to be electrically connected with bumps. The second semiconductor device is mounted on an area which is located on the backside surface of the first semiconductor device, the area having no bumps formed therein. The height of the second semiconductor device measured from the backside surface of the first semiconductor device is less than the height of the bumps. The second semiconductor device is mounted on the first semiconductor device such that the surface of the second semiconductor device provided with no terminals is joined to the backside surface of the first semiconductor device with an adhesive.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: March 13, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Shigeru Yamada, Yasushi Shiraishi
  • Patent number: 6145769
    Abstract: A thin ribbon cassette (16) is a set on a tape winding device and its vertical-direction position is fixed by a position restricting member (18) provided on a back of a cover and for an apparatus body. When the ribbon cassette (16) is thin in correspondence to a narrow width of an ink ribbon (15), a quantity of lowerig a ribbon winding top (5) engaged with a reel (16-1) of the cassette (16) is small. The biasing force of a clutch spring (7) which is compressed depending on the quantity of lowering of the ribbon winding top (5) is small, the force of a winding driver gear (6) which presses a clutch plate (4-1) through a felt member (12) is small, the frictional force of the felt member (12) is small, and the torque of the rotational shaft (4) is small. This torque is just suitable for winding a long and narrow ink ribbon having a corresponding small tensile strength.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: November 14, 2000
    Assignee: Casio Computer Co., Ltd.
    Inventors: Yasushi Shiraishi, Yoshiaki Mochizuki
  • Patent number: 6097083
    Abstract: A resin mold type semiconductor device, which is crack resistant and can be made relatively thin, includes a semiconductor chip, a lead member arranged in a manner such that an one side face of a head portion thereof touches a surface of the semiconductor chip, a wire for electrically connecting the surface of the semiconductor chip and another side face of the lead member, an adhesive member for adhering the one side face of the lead member and a peripheral face of the semiconductor chip, and a package for molding the semiconductor chip, a part of the lead, the wire and the adhesive member by synthetic resin. Further, the lead member may be provided with a concave portion in the one side face and possibly also a groove extending from the concave portion to an end of the lead.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: August 1, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Etsuo Yamada, Yasushi Shiraishi
  • Patent number: 6042038
    Abstract: A thin ribbon cassette (16) is set on a tape winding device and its vertical-direction position is fixed by a position restricting member (18) provided on a back of a cover for an apparatus body. When the ribbon cassette (16) is thin in correspondence to a narrow width of an ink ribbon (15), a quantity of lowering of a ribbon winding top (5) engaged with a reel (16-1) of the cassette (16) is small. The biasing force of a clutch spring (7) which is compressed depending on the quantity of lowering of the ribbon winding top (5) is small, the force of a winding drive gear (6) which presses a clutch plate (4-1) through a felt member (12) is small, the frictional force of the felt member (12) is small, and the torque of the rotational shaft (4) is small. This torque is just suitable for winding a long and narrow ink ribbon having a corresponding small tensile strength.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: March 28, 2000
    Assignee: Casio Computer Co., Ltd
    Inventor: Yasushi Shiraishi
  • Patent number: 6002181
    Abstract: A resin molded type semiconductor device has an inner portion sandwiched between two outer surfaces. The device includes a chip support with a first, inwardly facing surface and a second, outwardly facing surface. The device also includes a semiconductor element with a first, inwardly facing surface and a second, outwardly facing surface. The respective first surfaces of the chip support and semiconductor element are fixed to each other. A mold resin is provided to seal the entire semiconductor device except for the respective second surfaces of the chip support and semiconductor element which remain exposed as part of the two outer surfaces of the device, in order to keep the semiconductor device thin.
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: December 14, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Etsuo Yamada, Yasushi Shiraishi, Hiroshi Kawano, Shinji Ohuchi, Hidekazu Nasu
  • Patent number: 5969410
    Abstract: In a plastic packaged semiconductor device, a chip support formed on the same lead frame as leads is disposed so as to extend over the surface of a semiconductor element, the chip support is bonded and fixed to the surface of a polyimide wafer coat on the semiconductor element by means of an insulating tape, the leads are brought into contact with the polyimide wafer coat on the semiconductor element without being fixed, the leads and the electrodes of the semiconductor element are connected by means of gold wires, and these are packaged by a packaging material. Generation of crack in the sealing material thereby prevented, and the thickness of the plastic packaged semiconductor device is reduced.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: October 19, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Hiroshi Kawano, Etsuo Yamada, Yasushi Shiraishi
  • Patent number: 5810964
    Abstract: In a chemical mechanical polishing (CMP) device, a semiconductor wafer is held by a carrier with its surface to be polished facing upward. A polishing belt is fed from one reel and taken up by the other reel by way of pulleys, running in contact with the surface of the wafer to be polished. A conditioning pad conditions the front or polishing surface of the belt facing the wafer. A nozzle feeds polishing slurry to the rear of the belt not facing the wafer. A plurality of press rollers cause the slurry to exude from the front of the belt while pressing the slurry and belt against the surface of the wafer. The belt filters out impurities introduced into the slurry.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: September 22, 1998
    Assignee: NEC Corporation
    Inventor: Yasushi Shiraishi
  • Patent number: 5604356
    Abstract: The present invention provides an ohmic contact device which comprises: a first layer made of a first compound semiconductor having a first energy band gap; a superlattice in contact with the first layer, the superlattice having modulation-periods comprising alternating a first very thin layer made of the first compound semiconductor and a second very thin layer made of a second compound semiconductor having a second energy band gap being smaller than the first energy band gap, thicknesses of the first very thin layers being gradually reduced from an interface of the first layer to an opposite interface and thicknesses of the second very thin layers are gradually increased from the interface of the first layer to the opposite interface; a second layer made of the second compound semiconductor in contact with the superlattice; and a metal contact in contact with the second layer.
    Type: Grant
    Filed: July 5, 1995
    Date of Patent: February 18, 1997
    Assignee: NEC Corporation
    Inventor: Yasushi Shiraishi
  • Patent number: 5294565
    Abstract: An epitaxial growth method of a single crystal of III-V compound semiconductor on the surface of a semiconductor substrate by supplying a molecular beam of a group III source material and a molecular beam of a group V source material onto the surface of the substrate in a chamber held in vacuum. With this method, the molecular beams comprises a molecular beam of a first group III source material composed of an organic metal compound of a group III element not having a halogen, a molecular beam of a second group III source material having a halogen chemically bonded to atoms of the group III element, and a molecular beam of a group V source material making a compound semiconductor with the group III element of the first group III material. By setting a substrate temperature at, for example, about 500.degree. C. a single crystal of III-V compound semiconductor can be satisfactorily selectively grown.
    Type: Grant
    Filed: July 22, 1992
    Date of Patent: March 15, 1994
    Assignee: NEC Corporation
    Inventor: Yasushi Shiraishi