Patents by Inventor Yasutaka Nakashiba

Yasutaka Nakashiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220238651
    Abstract: The semiconductor device according to one embodiment includes a semiconductor substrate having a first surface and a second surface on an opposite side of the first surface, a gate insulating film formed on the first surface, a gate formed on the first surface via the gate insulating film, a source region formed in the first surface side of the semiconductor substrate, a body region formed so as to be in contact with the source region and including a channel region, a drain region formed in the second surface side of the semiconductor substrate, and a drift region formed so as to be in contact with the second surface side of the body region and the first surface side of the drain region. The semiconductor substrate has at least one concave portion formed in the second surface and being recessed toward the first surface.
    Type: Application
    Filed: December 16, 2021
    Publication date: July 28, 2022
    Inventors: Yasutaka NAKASHIBA, Akihiro SHIMOMURA, Masami SAWADA
  • Patent number: 11393782
    Abstract: A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: July 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutaka Nakashiba
  • Publication number: 20220173056
    Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 2, 2022
    Inventors: Tohru KAWAI, Yasutaka NAKASHIBA
  • Patent number: 11322668
    Abstract: A semiconductor device includes a substrate, an optical element, and a semiconductor element. The substrate includes a first region and a second region which are regions differing from each other. The optical element is formed in one of the first region and the second region. The electric element is formed in another of the first region and the second region. The first region includes a first insulating layer and a first semiconductor layer formed on the first insulating layer. The second region includes the first insulating layer, the first semiconductor layer, a second insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second insulating layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: May 3, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seigo Namioka, Yasutaka Nakashiba
  • Patent number: 11307479
    Abstract: A semiconductor device includes a first insulating layer, an optical modulator, and a multilayer wiring layer. The optical modulator is formed on the first insulating layer. The multilayer wiring layer is formed on the first insulating layer and including a wiring and a resistive element which are spaced apart from each other. The resistive element is formed without overlapping with the optical modulator in plan view. A material of the resistive element is at least one selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and silicon chromium.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Yasutaka Nakashiba
  • Patent number: 11262500
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: March 1, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba, Seigo Namioka, Tomoo Nakayama
  • Publication number: 20220020668
    Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 20, 2022
    Inventors: Tohru KAWAI, Yasutaka NAKASHIBA
  • Publication number: 20220013457
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element, and a multilayer wiring. The semiconductor element is formed on the semiconductor substrate. The multilayer wiring includes a wiring electrically connected with the semiconductor element, and a first inductor. The multilayer wiring is formed on the semiconductor substrate such that the multilayer wiring covers the semiconductor element. The first inductor is formed such that the first inductor electrically isolated from the wiring and is magnetically connected with the wiring.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 13, 2022
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA, Shinichi UCHIDA
  • Publication number: 20210366827
    Abstract: A semiconductor device includes: a first substrate; a multilayer wiring layer formed on the first substrate; a first inductor formed into a meander shape on the multilayer wiring layer in a plan view; and a second inductor formed into a meander shape on the multilayer wiring layer in a plain view, and arranged so as to be close to the first inductor in a plan view and not to overlap with the first inductor. A transformer is configured by the first inductor and the second inductor and, in a plan view, the first inductor and the second inductor extend along a first direction in which one side of the first substrate extends.
    Type: Application
    Filed: April 15, 2021
    Publication date: November 25, 2021
    Inventors: Shinichi UCHIDA, Yasutaka NAKASHIBA, Shinichi KUWABARA
  • Patent number: 11183471
    Abstract: A semiconductor device includes a semiconductor substrate, a multilayer wiring layer, a first inductor element, and a first capacitor element. The multilayer wiring layer is formed on the semiconductor substrate. The first inductor element and the first capacitor element are formed in the multilayer wiring layer. The first capacitor element is formed in the same layer as a layer in which the first inductor element is formed. The first capacitor element is formed inside the first inductor element in plan view.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 23, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutaka Nakashiba
  • Publication number: 20210356660
    Abstract: A semiconductor device includes a first insulating film, a first optical waveguide and a second optical waveguide. The first insulating film has a first surface and a second surface opposite to the first surface. The first optical waveguide is formed on the first surface of the first insulating film. The second optical waveguide is formed on the second surface of the first insulating film. The second optical waveguide, in plan view, overlaps with an end portion of the first optical waveguide without overlapping with another end portion of the first optical waveguide.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 18, 2021
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Publication number: 20210343641
    Abstract: A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.
    Type: Application
    Filed: March 3, 2021
    Publication date: November 4, 2021
    Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA
  • Patent number: 11145597
    Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: October 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Teruhiro Kuwajima
  • Patent number: 11137560
    Abstract: The semiconductor module includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes an optical device such as an optical waveguide and wiring formed over the optical device. The second semiconductor chip include semiconductor elements such as MISFET, and wiring formed over the semiconductor elements. A top surface of the first semiconductor chip is laminated with a top surface of the second semiconductor chip such that the first and second wirings are directly contacted with each other.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Patent number: 11139240
    Abstract: A semiconductor module includes a semiconductor chip including wiring formed over a semiconductor element such as a MISFET, a sealing resin part MR covering the semiconductor chip such that the wiring is exposed, and an inductor formed in redistribution wiring. The inductor overlaps with the sealing resin part covering at least a side surface of the semiconductor chip in plan view.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: October 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba
  • Publication number: 20210302801
    Abstract: A semiconductor device includes a first insulating layer, an optical modulator, and a multilayer wiring layer. The optical modulator is formed on the first insulating layer. The multilayer wiring layer is formed on the first insulating layer and including a wiring and a resistive element which are spaced apart from each other. The resistive element is formed without overlapping with the optical modulator in plan view. A material of the resistive element is at least one selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and silicon chromium.
    Type: Application
    Filed: March 25, 2020
    Publication date: September 30, 2021
    Inventors: Teruhiro KUWAJIMA, Yasutaka NAKASHIBA
  • Patent number: 11112624
    Abstract: A semiconductor device includes a first insulating layer, an optical waveguide, a first slab portion, a second insulating layer, and a conductive layer. The optical waveguide is formed on the first insulating layer and has a first side surface and a second side surface. The first slab portion is adjacent to the first side surface. The second insulating layer is formed on the optical waveguide. The conductive layer is formed on the second insulating layer. The optical waveguide has a first conductivity type. The first slab portion has first portion, second portion and third portion. The first portion has a second conductivity type opposite to the first conductivity type. The second portion is located farther from the optical waveguide than the first portion and has a first conductivity type. The third portion is formed between the optical waveguide and the second portion and has the first conductivity type.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: September 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Tohru Kawai
  • Patent number: 11079540
    Abstract: Two optical waveguides and an insulating film provided to cover the optical waveguides are formed over an insulating layer. Two wirings and a heater metal wire are formed over the insulating film via an insulating film different from the above insulating film. The latter insulating film is thinner than the former insulating film, and has a higher refractive index than the former insulating film. The leaked light from either of the two optical waveguides can be suppressed or prevented from being reflected by any one of the two wirings, the heater metal wire, and the like to travel again toward the two optical waveguides by utilizing the difference between the refractive indices of the two insulating films.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Watanuki, Yasutaka Nakashiba
  • Patent number: 11079539
    Abstract: According to the present invention, a first semiconductor chip includes a semiconductor substrate, an optical waveguide formed on an upper surface of the semiconductor substrate, and a concave portion formed in the semiconductor substrate in a region that differs from a region in which the optical waveguide is formed. A second semiconductor chip includes a compound semiconductor substrate, and a light emitting unit formed on an upper surface of the compound semiconductor substrate and emitting a laser beam. The second semiconductor chip is mounted in the concave portion of the first semiconductor chip, and a pedestal which is an insulating film is formed between a bottom surface of the concave portion and a back surface of the compound semiconductor substrate.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Publication number: 20210165160
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA, Seigo NAMIOKA, Tomoo NAKAYAMA