Patents by Inventor Yasutaka Nakashiba

Yasutaka Nakashiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11004830
    Abstract: The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: May 11, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Tetsuya Iida
  • Patent number: 11002997
    Abstract: A semiconductor device includes a first insulating layer, an optical waveguide formed on the first insulating layer, a fixed charge layer formed on the first insulating layer such that the fixed charge layer covers the optical waveguide, and a second insulating layer formed on the fixed charge layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 11, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seigo Namioka, Yasutaka Nakashiba
  • Patent number: 10991653
    Abstract: In a semiconductor device, a semiconductor substrate includes a bulk layer, a buried oxide layer provided in at least a partial region on the bulk layer, and a surface single crystal layer on the buried oxide layer. An inductor is provided above a main surface side of the semiconductor substrate on which the surface single crystal layer is disposed. To increase a Q value of the inductor, a ground shield is an impurity region formed in the bulk layer below the inductor and below the buried oxide layer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: April 27, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Uchida, Yasutaka Nakashiba
  • Publication number: 20210109383
    Abstract: A semiconductor device includes a first insulating layer, an optical waveguide, a first slab portion, a second insulating layer, and a conductive layer. The optical waveguide is formed on the first insulating layer and has a first side surface and a second side surface. The first slab portion is adjacent to the first side surface. The second insulating layer is formed on the optical waveguide. The conductive layer is formed on the second insulating layer. The optical waveguide has a first conductivity type. The first slab portion has first portion, second portion and third portion. The first portion has a second conductivity type opposite to the first conductivity type. The second portion is located farther from the optical waveguide than the first portion and has a first conductivity type. The third portion is formed between the optical waveguide and the second portion and has the first conductivity type.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 15, 2021
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka NAKASHIBA, Tohru KAWAI
  • Patent number: 10950543
    Abstract: The semiconductor device includes a first semiconductor substrate, a first wiring layer, a second wiring layer, a second semiconductor substrate, a first conductive portion, and a second conductive portion. The first wiring layer includes a first electrode pad and a first inductor electrically connected with each other. The second wiring layer includes a second inductor and a second electrode pad electrically connected with each other. The first conductive portion is formed in the second semiconductor substrate, the second wiring layer, and the first wiring layer so as to reach the first electrode pad from the back surface of the second semiconductor substrate. The second conductive portion is formed in the second semiconductor substrate and the second wiring layer so as to reach the second electrode pad from the back surface of the second semiconductor substrate. The first inductor and the second inductor are disposed so as to face each other.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: March 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba
  • Patent number: 10921515
    Abstract: A semiconductor device includes a substrate having a first surface and a second surface that have top and back relation, an insulating layer formed on the first surface of the substrate, and an optical waveguide formed on the insulating layer and formed of a semiconducting layer. A first opening is formed on the second surface of the substrate. The first opening overlaps the optical waveguide in plan view.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: February 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Shinichi Watanuki, Tohru Kawai
  • Patent number: 10921514
    Abstract: The semiconductor device includes an optical waveguide WG1 formed in a planar manner, and a three-dimensional optical waveguide WG2 optically connected with the optical waveguide WG1 and including a curved shape.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: February 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Patent number: 10895683
    Abstract: A semiconductor device includes an insulating layer, an optical waveguide formed on the insulating layer, a multilayer wiring layer formed on the insulating layer such that the multilayer wiring layer covers the optical waveguide, and a first inductor formed in the multilayer wiring layer.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: January 19, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Yasutaka Nakashiba
  • Patent number: 10895681
    Abstract: The semiconductor device has an optical waveguide formed on a substrate, a first conductor film formed in the same layer as the optical waveguide, an insulating film formed on the first conductor film, a second conductor film formed on the insulating film, and a first interlayer insulating film formed on the substrate so as to cover the optical waveguide and the second conductor film. The semiconductor device includes a first contact hole reaching the first conductor film, a second contact hole reaching the second conductor film, a first contact plug formed in the first contact hole, and a second contact plug formed in the second contact hole. The first conductor film is disposed between the first contact plugs and the board, but the second conductor film is not disposed between the first contact plugs and the board.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: January 19, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Watanuki, Yasutaka Nakashiba
  • Patent number: 10886213
    Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the coil is 7 ?m or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 ?m or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Yasutaka Nakashiba, Akira Matsumoto, Akio Ono, Tetsuya Iida
  • Publication number: 20200409231
    Abstract: A semiconductor device has a first semiconducting layer including an optical waveguide, a dielectric layer formed on the optical waveguide, and a conductive layer formed on the dielectric layer. A refractive index of a material of the conductive layer is smaller than a refractive index of a material of the first semiconductor layer.
    Type: Application
    Filed: May 12, 2020
    Publication date: December 31, 2020
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Publication number: 20200411434
    Abstract: A semiconductor device has a substrate, a first circuit, a first inductor, a second circuit and a second inductor IND2. The substrate includes a first region and a second region, which are regions different from each other. The first circuit is formed on the first region. The first inductor is electrically connected with the first circuit. The second circuit is formed on the second regions. The second inductor is electrically connected with the second circuit and formed to face the first inductor. A penetrating portion is formed in the substrate. The penetrating portion is formed such that the penetrating portion surrounds one or both of the first circuit and the second circuit in plan view.
    Type: Application
    Filed: May 12, 2020
    Publication date: December 31, 2020
    Inventor: Yasutaka NAKASHIBA
  • Publication number: 20200365508
    Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the coil is 7 ?m or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 ?m or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view.
    Type: Application
    Filed: August 4, 2020
    Publication date: November 19, 2020
    Inventors: Teruhiro KUWAJIMA, Yasutaka NAKASHIBA, Akira MATSUMOTO, Akio ONO, Tetsuya IIDA
  • Patent number: 10818591
    Abstract: A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 27, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Uchida, Yasutaka Nakashiba, Tetsuya Iida, Shinichi Kuwabara
  • Patent number: 10818650
    Abstract: The semiconductor module includes a semiconductor chip and a semiconductor chip. The semiconductor chip includes an optical device such as an optical waveguide, an optical receiver, and a grating coupler, and a wiring formed over the optical device. The semiconductor chip includes a semiconductor element such as a MISFET formed in the semiconductor substrate, and a wiring formed over the semiconductor element. a top surface of the semiconductor chip is laminated to a top surface of the semiconductor chip such that the wirings are in direct contact with each other. In the semiconductor substrate, a through hole having a circular shape in plan view is formed, in the through hole, an insulating film is formed as a cladding layer, and the semiconductor substrate surrounded by the through hole constitutes an optical waveguide.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: October 27, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Publication number: 20200295530
    Abstract: A semiconductor device includes a cladding layer and a first optical waveguide. The first optical waveguide is formed on the first cladding layer. An end surface of the first optical waveguide is inclined relative to a vertical line perpendicular to an upper surface of the cladding layer.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 17, 2020
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Publication number: 20200287108
    Abstract: A semiconductor device includes a substrate, an optical element, and a semiconductor element. The substrate includes a first region and a second region which are regions differing from each other. The optical element is formed in one of the first region and the second region. The electric element is formed in another of the first region and the second region. The first region includes a first insulating layer and a first semiconductor layer formed on the first insulating layer. The second region includes the first insulating layer, the first semiconductor layer, a second insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second insulating layer.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 10, 2020
    Inventors: Seigo NAMIOKA, Yasutaka NAKASHIBA
  • Publication number: 20200243443
    Abstract: A semiconductor module includes a semiconductor chip including wiring formed over a semiconductor element such as a MISFET, a sealing resin part MR covering the semiconductor chip such that the wiring is exposed, and an inductor formed in redistribution wiring. The inductor overlaps with the sealing resin part covering at least a side surface of the semiconductor chip in plan view.
    Type: Application
    Filed: January 15, 2020
    Publication date: July 30, 2020
    Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA
  • Patent number: 10720411
    Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Tetsuya Iida
  • Publication number: 20200201084
    Abstract: A semiconductor device includes a first insulating layer, an optical waveguide formed on the first insulating layer, a fixed charge layer formed on the first insulating layer such that the fixed charge layer covers the optical waveguide, and a second insulating layer formed on the fixed charge layer.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 25, 2020
    Inventors: Seigo NAMIOKA, Yasutaka NAKASHIBA