Abstract: A semiconductor device includes a cladding layer and a first optical waveguide. The first optical waveguide is formed on the first cladding layer. An end surface of the first optical waveguide is inclined relative to a vertical line perpendicular to an upper surface of the cladding layer.

Abstract: A multilayer wiring structure in which a plurality of conductive films and a plurality of interlayer dielectric films are laminated is formed so as to cover a main surface of a first semiconductor chip. The conductive films include conductive films to which a low voltage is applied and conductive films to which a high voltage is applied. The conductive films to which the low voltage is applied are located below the conductive films to which the high voltage is applied and closer to the main surface of a semiconductor substrate. The conductive films are arranged as conductive films of at least one layer between a first inductor to which the low voltage is applied and a second inductor to which the high voltage is applied.

Abstract: A semiconductor device includes a first semiconductor chip in which a first multilayer wiring structure including a first coil and a second coil is formed and a second semiconductor chip in which a second multilayer wiring structure including a third coil and a fourth coil is formed. The second semiconductor chip is joined to the first semiconductor chip such that the first coil (second coil) and the third coil (fourth coil) are overlapped and the second semiconductor chip does not have an offset structure with respect to the first semiconductor chip. The second semiconductor chip is joined to the first semiconductor chip such that it is not overlapped with a pad for the first semiconductor chip and a pad for the second semiconductor chip.

Abstract: A semiconductor substrate has a surface and a convex portion projecting upward from the surface. An n-type drift region has a portion located in the convex portion. The n?-type drain region has a higher n-type impurity concentration than the n-type drift region, and is arranged in the convex portion and on the n-type drift region such that the n?-type drain region and a gate electrode sandwich the n-type drift region in plan view.

Abstract: An electric fuse element has a first portion, a second portion arranged on one end of the first portion, and a third portion arranged on the other end of the first portion. A resistor element is arranged separately from the electric fuse element. A material of each of the electric fuse element and the resistor element has silicon metal or nickel chromium. The electric fuse element and the resistor element are arranged in an upper layer of the first wiring and in lower layer of the second wiring. A wiring width of the second portion and a wiring width of the third portion are larger than a wiring width of the first portion.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device to achieve both of a high breakdown voltage and a low on resistance are provided. A semiconductor substrate includes a convex portion protruding upward from a surface of the semiconductor substrate. An n-type drift region is arranged on the semiconductor substrate so as to be positioned between a gate electrode and an n+-type drain region in plan view, and has an impurity concentration lower than an impurity concentration of the n+-type drain region. A p-type resurf region is arranged in the convex portion and forms a pn junction with the n-type drift region.

Abstract: Variations of characteristics of a semiconductor device provided with a power MOSFET having a super junction structure are suppressed, and reliability of the semiconductor device is improved. A trench embedding an insulating film, which constitutes an insulator column therein, is formed in a first main surface of a semiconductor substrate whose crystal plane is a (110) plane. A crystal plane of a side surface of the trench in a short-side direction is a (111) plane, and a p-type diffusion layer constituting a p-column is formed in the above-mentioned side surface.

Abstract: A semiconductor device includes a first semiconductor chip, an adhesive layer that is formed on the first semiconductor chip, and a second semiconductor chip that is arranged on the first semiconductor chip via the adhesive layer. The first semiconductor chip has a first semiconductor substrate and a first wiring layer. The first wiring layer has a first inductor and a first electrode pad. The first wiring layer is formed on the first semiconductor substrate. The second semiconductor chip has a second wiring layer and a second semiconductor substrate. The second wiring layer is formed on the first wiring layer via the adhesive layer. The second semiconductor substrate is formed on the second wiring layer, and has a first opening. In a plan view, the first electrode pad is formed so as not to overlap with the second semiconductor chip, and a second electrode pad overlaps with the first opening.

Abstract: Reliability of a semiconductor device is improved by suppressing occurrence of variation in characteristics of the semiconductor device provided with a power MOSFET that has a super junction structure. A fixed charge layer FC is formed in a trench T2 that is formed in an upper surface of a semiconductor substrate SB and is adjacent to a p type body region BD and an n type drift layer DL. The fixed charge layer FC constituting a p column accumulates holes in the semiconductor substrate SB located at a side surface of the trench T2 to form a hole accumulation region HC.

Abstract: The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.

Abstract: A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.

Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.

Abstract: In semiconductor device, a field plate portion having a high concentration p-type semiconductor region, a low concentration p-type semiconductor region having a lower impurity concentration than the high concentration p-type semiconductor region and a high concentration n-type semiconductor region is provided. Then, the high concentration p-type semiconductor region is electrically connected to the source region while the high concentration n-type semiconductor region is electrically connected to the drain region.

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the gate dielectric film, a field plate portion which is integrally formed with the gate electrode, a step insulating film in contact with the field plate portion, a high dielectric constant film in contact with the step insulating film and having a higher dielectric constant than silicon.

Abstract: A semiconductor device has a first semiconducting layer including an optical waveguide, a dielectric layer formed on the optical waveguide, and a conductive layer formed on the dielectric layer. A refractive index of a material of the conductive layer is smaller than a refractive index of a material of the first semiconductor layer.

Abstract: A semiconductor device includes a first insulating film, a first optical waveguide and a second optical waveguide. The first insulating film has a first surface and a second surface opposite to the first surface. The first optical waveguide is formed on the first surface of the first insulating film. The second optical waveguide is formed on the second surface of the first insulating film. The second optical waveguide, in plan view, overlaps with an end portion of the first optical waveguide without overlapping with another end portion of the first optical waveguide.

Abstract: The semiconductor device according to one embodiment includes a semiconductor substrate having a first surface and a second surface on an opposite side of the first surface, a gate insulating film formed on the first surface, a gate formed on the first surface via the gate insulating film, a source region formed in the first surface side of the semiconductor substrate, a body region formed so as to be in contact with the source region and including a channel region, a drain region formed in the second surface side of the semiconductor substrate, and a drift region formed so as to be in contact with the second surface side of the body region and the first surface side of the drain region. The semiconductor substrate has at least one concave portion formed in the second surface and being recessed toward the first surface.

Abstract: A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.

Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.

Abstract: A semiconductor device includes a substrate, an optical element, and a semiconductor element. The substrate includes a first region and a second region which are regions differing from each other. The optical element is formed in one of the first region and the second region. The electric element is formed in another of the first region and the second region. The first region includes a first insulating layer and a first semiconductor layer formed on the first insulating layer. The second region includes the first insulating layer, the first semiconductor layer, a second insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second insulating layer.