Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor chip formation region, a chip internal circuit provided within the semiconductor chip formation region of the semiconductor substrate, a signal transmitting/receiving unit which is provided within the semiconductor chip formation region of the semiconductor substrate, transmits/receives a signal to/from an outside in a non-contact manner by one of electromagnetic induction and capacitive coupling, and transmits/receives a signal to/from the chip internal circuit through electrical connection to the chip internal circuit, and a power receiving inductor which has a diameter provided along an outer edge of the semiconductor chip formation region of the semiconductor substrate so as to surround the chip internal circuit and the signal transmitting/receiving unit, receives a power supply signal from the outside in the non-contact manner, and is electrically connected to the chip internal circuit.

Abstract: A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.

Abstract: To reduce a production cost of a semiconductor device and provide a semiconductor device having improved characteristics. A grating coupler has a plurality of projections separated from each other in an optical waveguide direction and a slab portion formed between any two of the projections adjacent to each other and formed integrally with them; a MOS optical modulator has a projection extending in the optical waveguide direction and slab portions formed on both sides of the projection, respectively, and formed integrally therewith. The projection of the grating coupler and the MOS optical modulator is formed of a first semiconductor layer, a second insulating layer, and a second semiconductor layer stacked successively on a first insulating layer, while the grating coupler and the MOS optical modulator each have a slab portion formed of the first semiconductor layer.

Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.

Abstract: An improvement is achieved in the reliability of a semiconductor device. A first semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a first insulating film formed over the insulating film. A second semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a second insulating film formed over the insulating film. The first insulating film forms an uppermost layer of the first semiconductor chip. The second insulating film forms an uppermost layer of the second semiconductor chip. Each of the first and second insulating films is made of a photosensitive resin film having an adhesive property.

Abstract: A semiconductor device including an optical waveguide and a p-type semiconductor portion is configured as follows. The optical waveguide includes: a first semiconductor layer formed on an insulating layer; an insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed on the insulating layer. The p-type semiconductor portion includes the first semiconductor layer. The film thickness of the p-type semiconductor portion is smaller than that of the optical waveguide. By forming the insulating layer between the first semiconductor layer and the second semiconductor layer, control of the film thicknesses of the optical waveguide and the p-type semiconductor portion is facilitated. Specifically, when the unnecessary second semiconductor layer is removed by etching in a step of forming the p-type semiconductor portion, the insulating layer which is the lower layer functions as an etching stopper, and the film thickness of the p-type semiconductor portion can be easily adjusted.

Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.

Abstract: An interposer includes a plurality of identical functional blocks arranged in the x direction, for example, and the functional blocks include a first region mounting a semiconductor chip, a second region mounting a light emitting element chip, a third region mounting a light receiving element chip, and a plurality of silicon waveguides. Then, the second and third regions are arranged between the first region and a first side along the x direction of the interposer. In addition, the plurality of silicon waveguides are arranged between the second region and the first side, and between the third region and the first side, extending from the second region toward the first side and from the third region toward the first side and are not formed between the functional blocks adjacent in the x direction.

Abstract: A Si photonics device includes: a first semiconductor chip; a second semiconductor chip having a laser diode and mounted on the first semiconductor chip; a third semiconductor chip taking in a laser beam emitted from the laser diode and mounted on the first semiconductor chip; and a resin layer disposed on the first semiconductor chip so as to face the second semiconductor chip. Further, the Si photonics device has: a bump electrode connecting the second semiconductor chip and an upper layer electrode pad provided on the resin layer of the first semiconductor chip; and a bump electrode connecting the first semiconductor chip and the third semiconductor chip, and the second semiconductor chip is mounted on the first semiconductor chip via the resin layer.

Abstract: A semiconductor device of the present invention includes, in a region 1C, a top electrode made by a semiconductor layer of an SOI substrate, a capacitive insulating film made by an insulating layer, a bottom electrode made by a supporting board, and a lead part (a high-concentration impurity region of an n type) of the bottom electrode coupled to the supporting board. An SOI transistor in a region 1B is formed over a main surface of the semiconductor layer over the insulating layer as a thin film, and threshold voltage can be adjusted by applying a voltage to a well arranged on the rear face side of the insulating layer.

Abstract: A circuit device, includes a semiconductor substrate, and a first inductor provided over said semiconductor substrate, and a first interconnect provided over said semiconductor substrate and coupled with first inductor.

Abstract: A semiconductor device including an optical waveguide and a p-type semiconductor portion is configured as follows. The optical waveguide includes: a first semiconductor layer formed on an insulating layer; an insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed on the insulating layer. The p-type semiconductor portion includes the first semiconductor layer. The film thickness of the p-type semiconductor portion is smaller than that of the optical waveguide. By forming the insulating layer between the first semiconductor layer and the second semiconductor layer, control of the film thicknesses of the optical waveguide and the p-type semiconductor portion is facilitated. Specifically, when the unnecessary second semiconductor layer is removed by etching in a step of forming the p-type semiconductor portion, the insulating layer which is the lower layer functions as an etching stopper, and the film thickness of the p-type semiconductor portion can be easily adjusted.

Abstract: In a semiconductor device, first dummy patterns including a different material from transmission lines (first optical waveguide and second optical waveguide) are formed in a first region close to the transmission lines, and second dummy patterns, which include the same material as the transmission lines and do not function as the transmission lines, are formed in a second region apart from the transmission lines.

Abstract: A semiconductor device includes: a first substrate; a surface insulating film formed over an upper surface of the first substrate; a BOX layer formed over the surface insulating film; an optical waveguide made of an SOI layer formed on the BOX layer; and a first interlayer insulating film formed over the BOX layer so as to cover the optical waveguide. The semiconductor device further includes: a trench formed in the surface insulating film and the first substrate below the optical waveguide; and a cladding layer made of a buried insulating film buried in the trench. A thickness of the BOX layer is 1 ?m or less, and a distance from an interface between the optical waveguide and the BOX layer to a bottom surface of the trench is 2 ?m or more.

Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.

Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.

Abstract: Provided is an SOI substrate which has a substrate, an insulating layer formed over the substrate, and a semiconductor layer formed over the insulating layer. Optical waveguides are formed in the semiconductor layer of the SOI substrate. This substrate has a low resistance semiconductor layer and a high resistance semiconductor layer thereover. Further, wirings which are formed through insulating films are provided on the optical waveguides. In this manner, the low resistance semiconductor layer is arranged in the surface part of the substrate of the insulating films, thereby restraining an eddy current generated in the substrate due to an electric signal transmitted through the wirings.

Abstract: An SOI substrate includes a base substrate, a polycrystalline silicon layer formed on the base substrate, an insulating layer formed on the polycrystalline silicon layer, and a semiconductor layer formed on the insulating layer, and optical waveguides are formed in the semiconductor layer of the SOI substrate. Thus, by arranging the polycrystalline silicon layer under the insulating layer, the insulating layer can be made thin. Since the polycrystalline silicon layer includes a plurality of grains (a mass of grains made of a single crystal Si), even when leakage of light is generated beyond the insulating layer, reflection (diffusion) of light can be suppressed. In addition, by arranging the polycrystalline silicon layer under the insulating layer, the insulating layer can be made thin, so that distortion of a substrate can be suppressed.

Abstract: A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.

Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.