Patents by Inventor Yasutaka Nakashiba

Yasutaka Nakashiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10418321
    Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Tetsuya Iida, Yasutaka Nakashiba
  • Patent number: 10416481
    Abstract: The performances of a semiconductor device are improved. The semiconductor device includes an insulation layer, an optical waveguide part formed over the insulation layer, and including a p type semiconductor region and an n type semiconductor region formed therein, and an interlayer insulation film formed over the insulation layer in such a manner as to cover the optical waveguide part. At the first portion of the optical waveguide part, in a cross sectional view perpendicular to the direction of extension of the optical waveguide part, the n type semiconductor region is arranged at the central part of the optical waveguide part, and the p type semiconductor region is arranged in such a manner as to surround the entire circumference of the n type semiconductor region.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tohru Kawai, Shinichi Watanuki, Yasutaka Nakashiba
  • Publication number: 20190273066
    Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.
    Type: Application
    Filed: February 19, 2019
    Publication date: September 5, 2019
    Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA, Tetsuya IIDA
  • Patent number: 10386586
    Abstract: A Si photonics device includes: a first semiconductor chip; a second semiconductor chip having a laser diode and mounted on the first semiconductor chip; a third semiconductor chip taking in a laser beam emitted from the laser diode and mounted on the first semiconductor chip; and a resin layer disposed on the first semiconductor chip so as to face the second semiconductor chip. Further, the Si photonics device has: a bump electrode connecting the second semiconductor chip and an upper layer electrode pad provided on the resin layer of the first semiconductor chip; and a bump electrode connecting the first semiconductor chip and the third semiconductor chip, and the second semiconductor chip is mounted on the first semiconductor chip via the resin layer.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: August 20, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Publication number: 20190206789
    Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the cod is 7 ?m or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 ?m or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view. Even if such wirings (linear wiring parts) are arranged under the coil, the characteristics (for example, RF characteristics) of the semiconductor device are not deteriorated. In addition, the area of the semiconductor device can be reduced or high integration of elements can be realized by laminating elements (for example, MOM capacitance elements and the like) having the coil and the linear wiring parts.
    Type: Application
    Filed: November 15, 2018
    Publication date: July 4, 2019
    Inventors: Teruhiro KUWAJIMA, Yasutaka NAKASHIBA, Akira MATSUMOTO, Akio ONO, Tetsuya IIDA
  • Publication number: 20190196110
    Abstract: An optical waveguide formed at the same layer as that of a microscopic optical device and a spot size converter largely different in size are integrally formed. A semiconductor device has an optical waveguide part functioning as a spot size converter. The optical waveguide part includes a plurality of optical waveguide bodies penetrating through an interlayer insulation layer in the thickness direction.
    Type: Application
    Filed: November 7, 2018
    Publication date: June 27, 2019
    Inventors: Yasutaka NAKASHIBA, Shinichi WATANUKI
  • Publication number: 20190196231
    Abstract: The performances of a semiconductor device are improved. The semiconductor device includes an insulation layer, an optical waveguide part formed over the insulation layer, and including a p type semiconductor region and an n type semiconductor region formed therein, and an interlayer insulation film formed over the insulation layer in such a manner as to cover the optical waveguide part. At the first portion of the optical waveguide part, in a cross sectional view perpendicular to the direction of extension of the optical waveguide part, the n type semiconductor region is arranged at the central part of the optical waveguide part, and the p type semiconductor region is arranged in such a manner as to surround the entire circumference of the n type semiconductor region.
    Type: Application
    Filed: November 6, 2018
    Publication date: June 27, 2019
    Inventors: Tohru KAWAI, Shinichi WATANUKI, Yasutaka NAKASHIBA
  • Publication number: 20190196099
    Abstract: Two optical waveguides and an insulating film provided to cover the optical waveguides are formed over an insulating layer. Two wirings and a heater metal wire are formed over the insulating film via an insulating film different from the above insulating film. The latter insulating film is thinner than the former insulating film, and has a higher refractive index than the former insulating film. The leaked light from either of the two optical waveguides can be suppressed or prevented from being reflected by any one of the two wirings, the heater metal wire, and the like to travel again toward the two optical waveguides by utilizing the difference between the refractive indices of the two insulating films.
    Type: Application
    Filed: November 7, 2018
    Publication date: June 27, 2019
    Inventors: Shinichi WATANUKI, Yasutaka NAKASHIBA
  • Publication number: 20190187370
    Abstract: In an optical waveguide section of an SIS type having a configuration of stacking a second semiconductor layer over a first semiconductor layer with a dielectric layer interposed, the first semiconductor layer is electrically coupled to a first electrode at a first lead-out section where the second semiconductor layer is not stacked. Further, the second semiconductor layer is electrically coupled to a second electrode at a second lead-out section not overlapping with the first semiconductor layer. As a result, when a contact hole for forming the second electrode is formed by dry etching, the dielectric layer between the first semiconductor layer and the second semiconductor layer is not damaged or broken and hence short-circuit failure between the first semiconductor layer and the second semiconductor layer can be prevented. The reliability of the optical waveguide section therefore can be improved.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 20, 2019
    Inventors: Yasutaka NAKASHIBA, Shinichi WATANUKI
  • Patent number: 10317769
    Abstract: In a semiconductor device connected to a first optical waveguide, a phase modulation unit, and a second optical waveguide in this order and having an optical modulator guiding light in a first direction, the phase modulation unit includes: a semiconductor layer whose length in the first direction is larger than a width in a second direction orthogonal to the first direction and which is made of monocrystalline silicon; a core part serving as an optical waveguide region formed on the semiconductor layer, and extending in the first direction; a pair of slab parts arranged on both sides of the core part in the second direction; a first electrode coupled with one of the slab parts; and a second electrode coupled with the other of the slab parts. The core part has a p type semiconductor region and an n type semiconductor region extending in the first direction, and the second direction coincides with a crystal orientation <100> of the semiconductor layer.
    Type: Grant
    Filed: April 28, 2018
    Date of Patent: June 11, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Watanuki, Yasutaka Nakashiba, Masaru Wakabayashi
  • Publication number: 20190165165
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Application
    Filed: January 31, 2019
    Publication date: May 30, 2019
    Inventors: Tohru KAWAI, Yasutaka NAKASHIBA, Yutaka AKIYAMA
  • Patent number: 10295743
    Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: May 21, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
  • Patent number: 10290577
    Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: May 14, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Teruhiro Kuwajima, Akira Matsumoto, Yasutaka Nakashiba, Takashi Iwadare
  • Patent number: 10236371
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: March 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tohru Kawai, Yasutaka Nakashiba, Yutaka Akiyama
  • Publication number: 20190072717
    Abstract: To provide a semiconductor device including a low-loss optical waveguide. The optical waveguide included in the semiconductor device has a core layer covered with first and second clad layers having respectively different refractive indices. A portion of the core layer is covered at a first ratio, that is, a ratio of the first clad layer to the second clad layer and at the same time, a second ratio, that is, a ratio of the second clad layer to the first clad layer. At this time, the first ratio and the second ratio are each a finite value more than 0.
    Type: Application
    Filed: July 16, 2018
    Publication date: March 7, 2019
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Patent number: 10197822
    Abstract: To reduce a production cost of a semiconductor device and provide a semiconductor device having improved characteristics. A grating coupler has a plurality of projections separated from each other in an optical waveguide direction and a slab portion formed between any two of the projections adjacent to each other and formed integrally with them; a MOS optical modulator has a projection extending in the optical waveguide direction and slab portions formed on both sides of the projection, respectively, and formed integrally therewith. The projection of the grating coupler and the MOS optical modulator is formed of a first semiconductor layer, a second insulating layer, and a second semiconductor layer stacked successively on a first insulating layer, while the grating coupler and the MOS optical modulator each have a slab portion formed of the first semiconductor layer.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: February 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Tetsuya Iida, Shinichi Watanuki
  • Publication number: 20190004342
    Abstract: In an optical waveguide supplied with electricity by using a heater, miniaturization of the device is achieved by enhancing heat dissipation efficiency and heat resistance. In a modulator including an optical waveguide formed on an insulating film, a first interlayer insulating film that covers the optical waveguide, a heater formed on the first interlayer insulating film, and a second interlayer insulating film that covers the heater, a heat conducting portion adjacent to the optical waveguide and the heater and penetrating the first and second interlayer insulating films is formed.
    Type: Application
    Filed: May 11, 2018
    Publication date: January 3, 2019
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA, Shinichi KUWABARA
  • Publication number: 20180366409
    Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.
    Type: Application
    Filed: April 16, 2018
    Publication date: December 20, 2018
    Inventors: Shinichi KUWABARA, Tetsuya IIDA, Yasutaka NAKASHIBA
  • Publication number: 20180341165
    Abstract: In a semiconductor device connected to a first optical waveguide, a phase modulation unit, and a second optical waveguide in this order and having an optical modulator guiding light in a first direction, the phase modulation unit includes: a semiconductor layer whose length in the first direction is larger than a width in a second direction orthogonal to the first direction and which is made of monocrystalline silicon; a core part serving as an optical waveguide region formed on the semiconductor layer, and extending in the first direction; a pair of slab parts arranged on both sides of the core part in the second direction; a first electrode coupled with one of the slab parts; and a second electrode coupled with the other of the slab parts. The core part has a p type semiconductor region and an n type semiconductor region extending in the first direction, and the second direction coincides with a crystal orientation <100> of the semiconductor layer.
    Type: Application
    Filed: April 28, 2018
    Publication date: November 29, 2018
    Inventors: Shinichi WATANUKI, Yasutaka NAKASHIBA, Masaru WAKABAYASHI
  • Patent number: 10120128
    Abstract: A semiconductor device includes: a first substrate; a surface insulating film formed over an upper surface of the first substrate; a BOX layer formed over the surface insulating film; an optical waveguide made of an SOI layer formed on the BOX layer; and a first interlayer insulating film formed over the BOX layer so as to cover the optical waveguide. The semiconductor device further includes: a trench formed in the surface insulating film and the first substrate below the optical waveguide; and a cladding layer made of a buried insulating film buried in the trench. A thickness of the BOX layer is 1 ?m or less, and a distance from an interface between the optical waveguide and the BOX layer to a bottom surface of the trench is 2 ?m or more.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Iida, Yasutaka Nakashiba