Patents by Inventor Yasuyuki Matsuoka
Yasuyuki Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240138150Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: December 28, 2023Publication date: April 25, 2024Applicant: Kioxia CorporationInventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO
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Patent number: 11903207Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: May 20, 2022Date of Patent: February 13, 2024Assignee: Kioxia CorporationInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Patent number: 11903205Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: May 13, 2022Date of Patent: February 13, 2024Assignee: Kioxia CorporationInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Publication number: 20220328517Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: May 20, 2022Publication date: October 13, 2022Applicant: Kioxia CorporationInventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO
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Publication number: 20220302166Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: May 13, 2022Publication date: September 22, 2022Applicant: Kioxia CorporationInventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO
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Patent number: 11374021Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: January 5, 2021Date of Patent: June 28, 2022Assignee: KIOXIA CORPORATIONInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Patent number: 11362106Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: January 5, 2021Date of Patent: June 14, 2022Assignee: KIOXIA CORPORATIONInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Publication number: 20210366011Abstract: An information processing method is executed by an information processing apparatus, and the information processing method includes listing, on a trading service, a first product designated by a first user, and upon receiving from a terminal of the first user an offer to barter the first product in exchange for a second product listed on the trading service by a second user, transmitting information indicating a shipment destination of the first product to the terminal of the first user, and transmitting information indicating a shipment destination of the second product to a terminal of the second user.Type: ApplicationFiled: May 17, 2021Publication date: November 25, 2021Inventors: Keisuke SOGAWA, Yasuyuki MATSUOKA, Mayumi NUMASAKI, Koji NOHARA, Hiroki SAGIUCHI, Motonori IWATA
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Publication number: 20210126011Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: January 5, 2021Publication date: April 29, 2021Applicant: Kioxia CorporationInventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO
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Publication number: 20210126012Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: January 5, 2021Publication date: April 29, 2021Applicant: Kioxia CorporationInventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO
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Publication number: 20210081921Abstract: An information processing method to be executed by an information processing apparatus includes providing a deferred payment service that includes a lump-sum payment to be liquidated in lump-sum within a predetermined period, and multiple times of payments to be liquidated respectively on a plurality of dates including a date within the predetermined period and dates after the predetermined period; receiving information of a first maximum amount to be liquidated by the deferred payment service within the predetermined period, designated by a user; and setting a second maximum amount, to be liquidated by one payment of the multiple times of payments, below the first maximum amount.Type: ApplicationFiled: September 14, 2020Publication date: March 18, 2021Inventors: Kan MIZUNO, Masato YAMAMOTO, Kazuho NAKAJIMA, Yasuyuki MATSUOKA, Yuuka YAMAJI, Koki KUSANO, Zhen CAO, Nobuo SUZUKI, Hisatomo YAMAMOTO
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Patent number: 10916559Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: January 11, 2019Date of Patent: February 9, 2021Assignee: Kioxia CorporationInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Publication number: 20200082499Abstract: To provide an information processing method capable of appropriately displaying an object, a computer-readable non-transitory storage medium having a program stored thereon, and an information processing device. An information processing method, executed by one or more processors included in an information processing device, including: specifying at least one of a first region in which an object is to be displayed and a second region in which display of the object is prohibited, the first region and the second region being included in a display region of a display device, based on a user operation; and displaying the object in the specified first region of the display device or displaying the object in a region other than the specified second region of the display device.Type: ApplicationFiled: September 11, 2019Publication date: March 12, 2020Inventors: Nobuo Suzuki, Yasuyuki Matsuoka
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Patent number: 10566175Abstract: A focus ring to be detachably attached to a top surface of an outer peripheral portion of a mounting table in a processing chamber, includes: an annular main body having a back surface to be attached to the top surface of the outer peripheral portion of the mounting table. And a thermally conductive sheet fixed to the annular main body, the thermally conductive sheet being interposed between the annular main body and the top surface of the outer peripheral portion of the mounting. The thermally conductive sheet is fixed as one unit to the annular main body by coating an unvulcanized rubber on one surface of the thermally conductive sheet, bringing said one surface into contact with the annular main body, and heating the thermally conductive sheet and the annular main body to vulcanize and to adhere the thermally conductive sheet to the annular main body.Type: GrantFiled: April 4, 2018Date of Patent: February 18, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Nobuyuki Nagayama, Naoyuki Satoh, Masahiko Oka, Yasuyuki Matsuoka
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Publication number: 20190148404Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: January 11, 2019Publication date: May 16, 2019Applicant: Toshiba Memory CorporationInventors: Masaru KITO, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Patent number: 10211219Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: August 2, 2017Date of Patent: February 19, 2019Assignee: Toshiba Memory CorporationInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Publication number: 20180240651Abstract: A focus ring to be detachably attached to a top surface of an outer peripheral portion of a mounting table in a processing chamber, includes: an annular main body having a back surface to be attached to the top surface of the outer peripheral portion of the mounting table. And a thermally conductive sheet fixed to the annular main body, the thermally conductive sheet being interposed between the annular main body and the top surface of the outer peripheral portion of the mounting. The thermally conductive sheet is fixed as one unit to the annular main body by coating an unvulcanized rubber on one surface of the thermally conductive sheet, bringing said one surface into contact with the annular main body, and heating the thermally conductive sheet and the annular main body to vulcanize and to adhere the thermally conductive sheet to the annular main body.Type: ApplicationFiled: April 4, 2018Publication date: August 23, 2018Applicant: TOKYO ELECTRON LIMITEDInventors: Nobuyuki NAGAYAMA, Naoyuki SATOH, Masahiko OKA, Yasuyuki MATSUOKA
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Publication number: 20170338244Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: August 2, 2017Publication date: November 23, 2017Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Patent number: 9748260Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: GrantFiled: May 29, 2015Date of Patent: August 29, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Patent number: 9453263Abstract: Provided is a method of detecting or quantifying a wheat species-specific DNA in a test sample by polymerase chain reaction. The method comprises a step of amplifying a nucleic acid molecule having a partial sequence of a nucleotide sequence identified as SEQ ID NO: 1 using a nucleic acid molecule in the test sample or a nucleic acid molecule extracted from the test sample as the template and using a primer pair capable of amplifying the partial sequence and a step of detecting or quantifying the amplified nucleic acid molecule.Type: GrantFiled: February 25, 2014Date of Patent: September 27, 2016Assignee: NISSHIN SEIFUN GROUP INC.Inventors: Kazumi Kitta, Satoshi Furui, Junichi Mano, Shinjiro Imai, Keiko Tanaka, Yasuyuki Matsuoka, Shinichiro Arami, Megumi Sato, Hiroyuki Haraguchi, Youichi Kurimoto