Patents by Inventor Yasuyuki Matsuoka

Yasuyuki Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10424570
    Abstract: A power conversion apparatus performs power conversion. The power conversion apparatus includes a semiconductor module and a cooler. The semiconductor module includes an insulated-gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor, and a lead frame. The insulated-gate bipolar transistor and the metal-oxide-semiconductor field-effect transistor are connected in parallel to each other and provided on the same lead frame. The cooler has a coolant flow passage. The coolant flow passage extends such that the coolant flow passage and the lead frame of the semiconductor module are opposed to each other. The semiconductor module is configured such that the metal-oxide-semiconductor field-effect transistor is not disposed further downstream than the insulated-gate bipolar transistor in a flow direction of a coolant in the coolant flow passage of the cooler.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: September 24, 2019
    Assignee: DENSO CORPORATION
    Inventors: Mitsunori Kimura, Hiroshi Shimizu, Kengo Mochiki, Yasuyuki Ohkouchi, Yuu Yamahira, Tetsuya Matsuoka, Kazuma Fukushima
  • Patent number: 10396651
    Abstract: A power conversion apparatus includes a semiconductor module including a semiconductor device and a control circuit unit controlling the semiconductor module. The semiconductor module has main and subsidiary semiconductor devices connected in parallel. The control circuit unit performs control such that the subsidiary semiconductor device is turned on after the main semiconductor device is turned on, and the main semiconductor device is turned off after the subsidiary semiconductor device is turned off. The control circuit unit performs control such that, one of the turn-on and turn-off switching timings has a switching speed faster than that of the other of the switching timings. The semiconductor module is configured such that, at a high-speed switching timing, an induction current directed to turn off the subsidiary semiconductor device is generated in a control terminal of the subsidiary semiconductor device depending on temporal change of a main current flowing to the main semiconductor device.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 27, 2019
    Assignee: DENSO CORPORATION
    Inventors: Kengo Mochiki, Mitsunori Kimura, Hiroshi Shimizu, Yasuyuki Ohkouchi, Yuu Yamahira, Tetsuya Matsuoka, Kazuma Fukushima
  • Patent number: 10347817
    Abstract: A lead-free piezoelectric ceramic composition including an alkali niobate/tantalate perovskite oxide main phase having piezoelectric properties and a different metal oxide. The mole ratio (Na/K) between Na (sodium) and K (potassium) in the main phase is 0.40<(Na/K)<3.0. The main phase has a crystal structure in which (i) first spots corresponding to a primitive lattice period and (ii) second spots corresponding to the lattice period two times the primitive lattice period and being weaker than the first spots appear in an electron beam diffraction image entering from the <100> direction with the main phase represented as a pseudo-cubic crystal system. Also, the area ratio of a crystal phase reflecting the second spots in the main phase is 33% or less, and the maximum grain size of crystals reflecting the second spots in the main phase is 25 nm or less.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: July 9, 2019
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Hisashi Kozuka, Hideto Yamada, Takayuki Matsuoka, Kazuaki Kitamura, Masato Yamazaki, Toshiaki Kurahashi, Takashi Kasashima, Yasuyuki Okimura, Kazushige Ohbayashi
  • Patent number: 10340441
    Abstract: A lead-free piezoelectric ceramic composition including an alkali niobate/tantalate perovskite oxide main phase having piezoelectric properties and a different metal oxide subphase. The mole ratio (Na/K) between Na (sodium) and K (potassium) in the main phase assumes a value in a range represented by 0.40<(Na/K)<3.0. The main phase has a crystal structure in which (i) first spots corresponding to a primitive lattice period and (ii) second spots corresponding to the lattice period two times the primitive lattice period and being weaker than the first spots appear in an electron beam diffraction image entering from the <100> direction with the main phase represented as a pseudo-cubic crystal system.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: July 2, 2019
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Hisashi Kozuka, Hideto Yamada, Takayuki Matsuoka, Kazuaki Kitamura, Masato Yamazaki, Toshiaki Kurahashi, Takashi Kasashima, Yasuyuki Okimura, Kazushige Ohbayashi
  • Publication number: 20190148404
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Application
    Filed: January 11, 2019
    Publication date: May 16, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masaru KITO, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 10211219
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: February 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Publication number: 20180240651
    Abstract: A focus ring to be detachably attached to a top surface of an outer peripheral portion of a mounting table in a processing chamber, includes: an annular main body having a back surface to be attached to the top surface of the outer peripheral portion of the mounting table. And a thermally conductive sheet fixed to the annular main body, the thermally conductive sheet being interposed between the annular main body and the top surface of the outer peripheral portion of the mounting. The thermally conductive sheet is fixed as one unit to the annular main body by coating an unvulcanized rubber on one surface of the thermally conductive sheet, bringing said one surface into contact with the annular main body, and heating the thermally conductive sheet and the annular main body to vulcanize and to adhere the thermally conductive sheet to the annular main body.
    Type: Application
    Filed: April 4, 2018
    Publication date: August 23, 2018
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Nobuyuki NAGAYAMA, Naoyuki SATOH, Masahiko OKA, Yasuyuki MATSUOKA
  • Publication number: 20170338244
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Application
    Filed: August 2, 2017
    Publication date: November 23, 2017
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 9748260
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: August 29, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 9453263
    Abstract: Provided is a method of detecting or quantifying a wheat species-specific DNA in a test sample by polymerase chain reaction. The method comprises a step of amplifying a nucleic acid molecule having a partial sequence of a nucleotide sequence identified as SEQ ID NO: 1 using a nucleic acid molecule in the test sample or a nucleic acid molecule extracted from the test sample as the template and using a primer pair capable of amplifying the partial sequence and a step of detecting or quantifying the amplified nucleic acid molecule.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 27, 2016
    Assignee: NISSHIN SEIFUN GROUP INC.
    Inventors: Kazumi Kitta, Satoshi Furui, Junichi Mano, Shinjiro Imai, Keiko Tanaka, Yasuyuki Matsuoka, Shinichiro Arami, Megumi Sato, Hiroyuki Haraguchi, Youichi Kurimoto
  • Patent number: 9447475
    Abstract: Provided is a method of detecting or quantifying a wheat species-specific DNA in a test sample by polymerase chain reaction. The method comprises a step of amplifying a nucleic acid molecule having at partial sequence of a nucleotide sequence identified as SEQ ID NO: 1 using a nucleic acid molecule in the test sample or a nucleic acid molecule extracted from the test sample as the template and using a primer pair capable of amplifying the partial sequence and a step of detecting or quantifying the amplified nucleic acid molecule.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 20, 2016
    Assignee: NISSHIN SEIFUN GROUP INC.
    Inventors: Kazumi Kitta, Satoshi Furui, Junichi Mano, Shinjiro Imai, Keiko Tanaka, Yasuyuki Matsuoka, Shinichiro Arami, Megumi Sato, Hiroyuki Haraguchi, Youichi Kurimoto
  • Patent number: 9273362
    Abstract: Provided is a method of detecting or quantifying a wheat species-specific DNA in a test sample by polymerase chain reaction. The method comprises a step of amplifying a nucleic acid molecule having a partial sequence of a nucleotide sequence identified as SEQ ID NO: 1 using a nucleic acid molecule in the test sample or a nucleic acid molecule extracted from the test sample as the template and using a primer pair capable of amplifying the partial sequence and a step of detecting or quantifying the amplified nucleic acid molecule.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: March 1, 2016
    Assignee: NISSHIN SEIFUN GROUP INC.
    Inventors: Kazumi Kitta, Satoshi Furui, Junichi Mano, Shinjiro Imai, Keiko Tanaka, Yasuyuki Matsuoka, Shinichiro Arami, Megumi Sato, Hiroyuki Haraguchi, Youichi Kurimoto
  • Publication number: 20150372006
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 24, 2015
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 9064735
    Abstract: A nonvolatile semiconductor memory device that has a new structure is provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device has a plurality of memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 23, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Publication number: 20150114567
    Abstract: A focus ring to be detachably attached to a top surface of an outer peripheral portion of a mounting table in a processing chamber, includes: an annular main body having a back surface to be attached to the top surface of the outer peripheral portion of the mounting table. And a thermally conductive sheet fixed to the annular main body, the thermally conductive sheet being interposed between the annular main body and the top surface of the outer peripheral portion of the mounting. The thermally conductive sheet is fixed as one unit to the annular main body by coating an unvulcanized rubber on one surface of the thermally conductive sheet, bringing said one surface into contact with the annular main body, and heating the thermally conductive sheet and the annular main body to vulcanize and to adhere the thermally conductive sheet to the annular main body.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 30, 2015
    Applicants: Greene, Tweed Technologies, Inc., TOKYO ELECTRON LIMITED
    Inventors: Nobuyuki NAGAYAMA, Naoyuki SATOH, Masahiko OKA, Yasuyuki MATSUOKA
  • Patent number: 8865433
    Abstract: Disclosed are: a method for detecting common wheat among from wheat varieties contained in a sample of interest such as a food raw material or a processed food specifically, with high sensitivity, and in a qualitative and/or quantitative manner; a method for discriminating between common wheat and a wheat variety other than common wheat (e.g., durum wheat) contained in a food raw material or a processed food and detecting the common wheat in a qualitative and/or quantitative manner; and a primer set, a nucleic acid probe, and a detection kit, each of which can be used in the methods employing a PCR method.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: October 21, 2014
    Assignees: Nippon Flour Mills Co., Ltd, Nisshin Seifun Group Inc
    Inventors: Kazumi Kitta, Satoshi Furui, Junichi Mano, Yasuyuki Matsuoka, Shinichiro Arami, Megumi Sato, Hiroyuki Haraguchi, Youichi Kurimoto, Shinjiro Imai, Keiko Tanaka
  • Publication number: 20140287405
    Abstract: Provided is a method of detecting or quantifying a wheat species-specific DNA in a test sample by polymerase chain reaction. The method comprises a step of amplifying a nucleic acid molecule having a partial sequence of a nucleotide sequence identified as SEQ ID NO: 1 using a nucleic acid molecule in the test sample or a nucleic acid molecule extracted from the test sample as the template and using a primer pair capable of amplifying the partial sequence and a step of detecting or quantifying the amplified nucleic acid molecule.
    Type: Application
    Filed: February 25, 2014
    Publication date: September 25, 2014
    Applicant: Nisshin Seifun Group Inc.
    Inventors: Kazumi KITTA, Satoshi FURUI, Junichi MANO, Shinjiro IMAI, Keiko TANAKA, Yasuyuki MATSUOKA, Shinichiro ARAMI, Megumi SATO, Hiroyuki HARAGUCHI, Youichi KURIMOTO
  • Publication number: 20140288289
    Abstract: Provided is a method of detecting or quantifying a wheat species-specific DNA in a test sample by polymerase chain reaction. The method comprises a step of amplifying a nucleic acid molecule having at partial sequence of a nucleotide sequence identified as SEQ ID NO: 1 using a nucleic acid molecule in the test sample or a nucleic acid molecule extracted from the test sample as the template and using a primer pair capable of amplifying the partial sequence and a step of detecting or quantifying the amplified nucleic acid molecule.
    Type: Application
    Filed: February 25, 2014
    Publication date: September 25, 2014
    Applicant: Nisshin Seifun Group Inc.
    Inventors: Kazumi KITTA, Satoshi FURUI, Junichi MANO, Shinjiro IMAI, Keiko TANAKA, Yasuyuki MATSUOKA, Shinichiro ARAMI, Megumi SATO, Hiroyuki HARAGUCHI, Youichi KURIMOTO
  • Patent number: 8551838
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: October 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 8426976
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a columnar semiconductor layer extending in a direction perpendicular to a substrate; a plurality of conductive layers formed at a sidewall of the columnar semiconductor layer via memory layers; and interlayer insulation layers formed above of below the conductive layers. A sidewall of the conductive layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes larger at lower position thereof than at upper position thereof. While, a sidewall of the interlayer insulation layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes smaller at lower position thereof than at upper position thereof.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: April 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Megumi Ishiduki, Hideaki Aochi, Ryota Katsumata, Hiroyasu Tanaka, Masaru Kidoh, Masaru Kito, Yoshiaki Fukuzumi, Yosuke Komori, Yasuyuki Matsuoka