Patents by Inventor Yasuyuki Matsuoka

Yasuyuki Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9447475
    Abstract: Provided is a method of detecting or quantifying a wheat species-specific DNA in a test sample by polymerase chain reaction. The method comprises a step of amplifying a nucleic acid molecule having at partial sequence of a nucleotide sequence identified as SEQ ID NO: 1 using a nucleic acid molecule in the test sample or a nucleic acid molecule extracted from the test sample as the template and using a primer pair capable of amplifying the partial sequence and a step of detecting or quantifying the amplified nucleic acid molecule.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 20, 2016
    Assignee: NISSHIN SEIFUN GROUP INC.
    Inventors: Kazumi Kitta, Satoshi Furui, Junichi Mano, Shinjiro Imai, Keiko Tanaka, Yasuyuki Matsuoka, Shinichiro Arami, Megumi Sato, Hiroyuki Haraguchi, Youichi Kurimoto
  • Patent number: 9273362
    Abstract: Provided is a method of detecting or quantifying a wheat species-specific DNA in a test sample by polymerase chain reaction. The method comprises a step of amplifying a nucleic acid molecule having a partial sequence of a nucleotide sequence identified as SEQ ID NO: 1 using a nucleic acid molecule in the test sample or a nucleic acid molecule extracted from the test sample as the template and using a primer pair capable of amplifying the partial sequence and a step of detecting or quantifying the amplified nucleic acid molecule.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: March 1, 2016
    Assignee: NISSHIN SEIFUN GROUP INC.
    Inventors: Kazumi Kitta, Satoshi Furui, Junichi Mano, Shinjiro Imai, Keiko Tanaka, Yasuyuki Matsuoka, Shinichiro Arami, Megumi Sato, Hiroyuki Haraguchi, Youichi Kurimoto
  • Publication number: 20150372006
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 24, 2015
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 9064735
    Abstract: A nonvolatile semiconductor memory device that has a new structure is provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device has a plurality of memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 23, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Publication number: 20150114567
    Abstract: A focus ring to be detachably attached to a top surface of an outer peripheral portion of a mounting table in a processing chamber, includes: an annular main body having a back surface to be attached to the top surface of the outer peripheral portion of the mounting table. And a thermally conductive sheet fixed to the annular main body, the thermally conductive sheet being interposed between the annular main body and the top surface of the outer peripheral portion of the mounting. The thermally conductive sheet is fixed as one unit to the annular main body by coating an unvulcanized rubber on one surface of the thermally conductive sheet, bringing said one surface into contact with the annular main body, and heating the thermally conductive sheet and the annular main body to vulcanize and to adhere the thermally conductive sheet to the annular main body.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 30, 2015
    Applicants: Greene, Tweed Technologies, Inc., TOKYO ELECTRON LIMITED
    Inventors: Nobuyuki NAGAYAMA, Naoyuki SATOH, Masahiko OKA, Yasuyuki MATSUOKA
  • Patent number: 8865433
    Abstract: Disclosed are: a method for detecting common wheat among from wheat varieties contained in a sample of interest such as a food raw material or a processed food specifically, with high sensitivity, and in a qualitative and/or quantitative manner; a method for discriminating between common wheat and a wheat variety other than common wheat (e.g., durum wheat) contained in a food raw material or a processed food and detecting the common wheat in a qualitative and/or quantitative manner; and a primer set, a nucleic acid probe, and a detection kit, each of which can be used in the methods employing a PCR method.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: October 21, 2014
    Assignees: Nippon Flour Mills Co., Ltd, Nisshin Seifun Group Inc
    Inventors: Kazumi Kitta, Satoshi Furui, Junichi Mano, Yasuyuki Matsuoka, Shinichiro Arami, Megumi Sato, Hiroyuki Haraguchi, Youichi Kurimoto, Shinjiro Imai, Keiko Tanaka
  • Publication number: 20140288289
    Abstract: Provided is a method of detecting or quantifying a wheat species-specific DNA in a test sample by polymerase chain reaction. The method comprises a step of amplifying a nucleic acid molecule having at partial sequence of a nucleotide sequence identified as SEQ ID NO: 1 using a nucleic acid molecule in the test sample or a nucleic acid molecule extracted from the test sample as the template and using a primer pair capable of amplifying the partial sequence and a step of detecting or quantifying the amplified nucleic acid molecule.
    Type: Application
    Filed: February 25, 2014
    Publication date: September 25, 2014
    Applicant: Nisshin Seifun Group Inc.
    Inventors: Kazumi KITTA, Satoshi FURUI, Junichi MANO, Shinjiro IMAI, Keiko TANAKA, Yasuyuki MATSUOKA, Shinichiro ARAMI, Megumi SATO, Hiroyuki HARAGUCHI, Youichi KURIMOTO
  • Publication number: 20140287405
    Abstract: Provided is a method of detecting or quantifying a wheat species-specific DNA in a test sample by polymerase chain reaction. The method comprises a step of amplifying a nucleic acid molecule having a partial sequence of a nucleotide sequence identified as SEQ ID NO: 1 using a nucleic acid molecule in the test sample or a nucleic acid molecule extracted from the test sample as the template and using a primer pair capable of amplifying the partial sequence and a step of detecting or quantifying the amplified nucleic acid molecule.
    Type: Application
    Filed: February 25, 2014
    Publication date: September 25, 2014
    Applicant: Nisshin Seifun Group Inc.
    Inventors: Kazumi KITTA, Satoshi FURUI, Junichi MANO, Shinjiro IMAI, Keiko TANAKA, Yasuyuki MATSUOKA, Shinichiro ARAMI, Megumi SATO, Hiroyuki HARAGUCHI, Youichi KURIMOTO
  • Patent number: 8551838
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: October 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 8426276
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: April 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 8426976
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a columnar semiconductor layer extending in a direction perpendicular to a substrate; a plurality of conductive layers formed at a sidewall of the columnar semiconductor layer via memory layers; and interlayer insulation layers formed above of below the conductive layers. A sidewall of the conductive layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes larger at lower position thereof than at upper position thereof. While, a sidewall of the interlayer insulation layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes smaller at lower position thereof than at upper position thereof.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: April 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Megumi Ishiduki, Hideaki Aochi, Ryota Katsumata, Hiroyasu Tanaka, Masaru Kidoh, Masaru Kito, Yoshiaki Fukuzumi, Yosuke Komori, Yasuyuki Matsuoka
  • Patent number: 8350314
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising a plurality of memory strings, each of the memory strings being constituted with a plurality of electrically erasable memory cells being serially connected each other, the memory strings comprising: a columnar semiconductor layer perpendicularly extending toward a substrate; a plurality of conductive layers being formed in parallel to the substrate and including a first space between a sidewall of the columnar semiconductor layers; and characteristic change layer being formed on the sidewall of the columnar semiconductor layer faced to the first space or a sidewall of the conductive layer faced to the first space and changing characteristics accompanying with applied voltage; wherein the plurality of the conductive layers have a function of a relative movement to a prescribed direction for the columnar semiconductor layer.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 8330216
    Abstract: A non-volatile semiconductor memory device includes a first columnar semiconductor layer and a plurality of first conductive layers formed such that a charge storage layer for storing charges is sandwiched between the first conductive layers and the first columnar semiconductor layer. Also, the non-volatile semiconductor memory device includes a second columnar semiconductor layer and a second conductive layer formed such that an insulating layer is sandwiched between the second conductive layer and the second columnar semiconductor layer, the second conductive layer being repeatedly provided in a line form by providing a certain interval in a first direction perpendicular to a laminating direction. A first sidewall conductive layer being in contact with the second conductive layer and extending in the first direction is formed on a sidewall along a longitudinal direction of the second conductive layer.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: December 11, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Komori, Masaru Kito, Megumi Ishiduki, Ryota Katsumata, Hiroyasu Tanaka, Masaru Kidoh, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 8293601
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20120264128
    Abstract: Disclosed are: a method for detecting common wheat among from wheat varieties contained in a sample of interest such as a food raw material or a processed food specifically, with high sensitivity, and in a qualitative and/or quantitative manner; a method for discriminating between common wheat and a wheat variety other than common wheat (e.g., durum wheat) contained in a food raw material or a processed food and detecting the common wheat in a qualitative and/or quantitative manner; and a primer set, a nucleic acid probe, and a detection kit, each of which can be used in the methods employing a PCR method.
    Type: Application
    Filed: December 17, 2010
    Publication date: October 18, 2012
    Applicants: NISSHIN SEIFUN GROUP INC., NIPPON FLOUR MILLS CO., LTD
    Inventors: Kazumi Kitta, Satoshi Furui, Junichi Mano, Yasuyuki Matsuoka, Shinichiro Arami, Megumi Sato, Hiroyuki Haraguchi, Youichi Kurimoto, Shinjiro Imai, Keiko Tanaka
  • Publication number: 20120258464
    Abstract: Provided is a method of detecting or quantifying a wheat species-specific DNA in a test sample by polymerase chain reaction. The method comprises a step of amplifying a nucleic acid molecule having a partial sequence of a nucleotide sequence identified as SEQ ID NO: 1 using a nucleic acid molecule in the test sample or a nucleic acid molecule extracted from the test sample as the template and using a primer pair capable of amplifying the partial sequence and a step of detecting or quantifying the amplified nucleic acid molecule.
    Type: Application
    Filed: December 17, 2010
    Publication date: October 11, 2012
    Inventors: Kazumi Kitta, Satoshi Furui, Junichi Mano, Shinjiro Imai, Keiko Tanaka, Yasuyuki Matsuoka, Shinichiro Arami, Megumi Sato, Hiroyuki Haraguchi, Youichi Kurimoto
  • Patent number: 8253187
    Abstract: A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: August 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu Tanaka, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kido, Hideaki Aochi, Mitsuru Sato, Yasuyuki Matsuoka
  • Patent number: 8237211
    Abstract: A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: August 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Akihiro Nitayama, Hideaki Aochi, Hitoshi Ito, Yasuyuki Matsuoka
  • Patent number: 8193571
    Abstract: A stacked body is formed on a silicon substrate by stacking a plurality of insulating films and a plurality of electrode films alternately and through-holes are formed to extend in the stacking direction. Next, gaps are formed between the electrode films using etching the insulating films via the through-holes. Charge storage layers are formed along side faces of the through-holes and inner faces of the gaps, and silicon pillars are filled into the through-holes. Thereby, a nonvolatile semiconductor memory device is manufactured.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Yasuyuki Matsuoka
  • Publication number: 20120135595
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.
    Type: Application
    Filed: February 3, 2012
    Publication date: May 31, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru Kito, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka