Patents by Inventor Yasuyuki Matsuoka
Yasuyuki Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8178917Abstract: A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction.Type: GrantFiled: March 20, 2009Date of Patent: May 15, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Hideaki Aochi, Megumi Ishiduki, Yasuyuki Matsuoka
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Patent number: 8154103Abstract: A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.Type: GrantFiled: December 17, 2010Date of Patent: April 10, 2012Assignee: Kabushiki Kaisha TohibaInventors: Hiroyasu Tanaka, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Yoshiaki Fukuzumi, Masaru Kito, Yasuyuki Matsuoka
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Patent number: 8148789Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.Type: GrantFiled: October 29, 2008Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
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Publication number: 20110287597Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: March 31, 2011Publication date: November 24, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Publication number: 20110284947Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: August 4, 2011Publication date: November 24, 2011Inventors: Masaru KITO, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Patent number: 8048798Abstract: A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall insulating layer on a side wall facing the first hole; forming a sacrificing layer so that the sacrificing layer infills the first hole; forming a second conductive layer on an upper layer of the sacrificing layer so that the second conductive layer is sandwiched by the second insulating layer in an up-down direction; forming a second hole on a position which matches with the first hole so that the second hole penetrates the second insulating layer and the second conductive layer; forming a second side wall insulating layer on a side wall facing the second hole; removing the sacrificing layer after the formation of the second side wall insulating layer; and forming a semiconductor layer so thatType: GrantFiled: February 20, 2009Date of Patent: November 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Yasuyuki Matsuoka
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Patent number: 8013383Abstract: A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.Type: GrantFiled: February 20, 2009Date of Patent: September 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Akihiro Nitayama, Hitoshi Ito, Yasuyuki Matsuoka
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Publication number: 20110111579Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.Type: ApplicationFiled: January 20, 2011Publication date: May 12, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
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Patent number: 7936004Abstract: A nonvolatile semiconductor memory device includes a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; a second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory string and the first to nth electrodes of at least two other memory strings which are adjacent to the memory string in two directions are shared as first to nth conductor layers spread in two dimensions.Type: GrantFiled: January 18, 2007Date of Patent: May 3, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Patent number: 7927926Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.Type: GrantFiled: October 20, 2010Date of Patent: April 19, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
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Publication number: 20110084331Abstract: A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.Type: ApplicationFiled: December 17, 2010Publication date: April 14, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyasu Tanaka, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Yoshiaki Fukuzumi, Masaru Kito, Yasuyuki Matsuoka
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Patent number: 7910979Abstract: The invention provides a nonvolatile semiconductor memory device comprising a plurality of memory strings each including a plurality of electrically programmable memory cells connected in series. The memory string includes a semiconductor pillar, an insulator formed around the circumference of the semiconductor pillar, and first through nth electrodes to be turned into gate electrodes (n denotes a natural number equal to 2 or more) formed around the circumference of the insulator. It also includes interlayer electrodes formed in regions between the first through nth electrodes around the circumference of the insulator.Type: GrantFiled: July 8, 2008Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yasuyuki Matsuoka, Yoshiaki Fukuzumi, Hideaki Aochi
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Patent number: 7910432Abstract: Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction.Type: GrantFiled: February 26, 2009Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Masaru Kidoh, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
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Patent number: 7902591Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.Type: GrantFiled: October 3, 2008Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
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Patent number: 7888789Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.Type: GrantFiled: March 25, 2005Date of Patent: February 15, 2011Assignee: Panasonic CorporationInventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
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Publication number: 20110033995Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.Type: ApplicationFiled: October 20, 2010Publication date: February 10, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Ryota KATSUMATA, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
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Patent number: 7868416Abstract: A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.Type: GrantFiled: May 4, 2010Date of Patent: January 11, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Yoshiaki Fukuzumi, Masaru Kito, Yasuyuki Matsuoka
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Patent number: 7859066Abstract: A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.Type: GrantFiled: June 17, 2008Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka
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Patent number: 7847334Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.Type: GrantFiled: March 13, 2009Date of Patent: December 7, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
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Patent number: 7847342Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate and having a first hollow extending downward from its upper end; a first insulation layer formed in contact with the outer wall of the first columnar semiconductor layer; a second insulation layer formed on the inner wall of the first columnar semiconductor layer so as to leave the first hollow; and a plurality of first conductive layers formed to sandwich the first insulation layer with the first columnar semiconductor layer and functioning as control electrodes of the memory cells.Type: GrantFiled: November 28, 2008Date of Patent: December 7, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka