Patents by Inventor Yasuyuki Matsuoka
Yasuyuki Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7821058Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a columnar semiconductor; a charge storage insulating film including: a first insulating film formed around the columnar semiconductor, a charge storage film formed around the first insulating film, and a second insulating film formed around the charge storage film; an electrode extending two-dimensionally to surround the charge storage insulating film, the electrode having a groove; and a metal silicide formed on a sidewall of the groove.Type: GrantFiled: January 8, 2008Date of Patent: October 26, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hideaki Aochi, Hiroyasu Tanaka, Yasuyuki Matsuoka, Yoshio Ozawa, Mitsuru Sato
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Patent number: 7795092Abstract: A semiconductor memory device includes gate electrodes extending in a first direction above a surface of a substrate. The semiconductor memory device also includes a reinforcement insulation film formed in a line shape and extending in a second direction crossing the gate electrodes in a plane view viewed from above the surface of the substrate, and connected to adjacent gate electrodes. Further, the semiconductor memory device includes an interlayer dielectric film provided between the adjacent gate electrodes, and having a void inside.Type: GrantFiled: June 3, 2008Date of Patent: September 14, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yasuyuki Matsuoka, Masaru Kito, Hideaki Aochi, Takayuki Okamura
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Publication number: 20100219465Abstract: A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.Type: ApplicationFiled: May 4, 2010Publication date: September 2, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyasu TANAKA, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Yoshiaki Fukuzumi, Masaru Kito, Yasuyuki Matsuoka
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Patent number: 7768063Abstract: A semiconductor device comprising: a semiconductor substrate; a first conductive layer provided on a surface of the substrate and serving as one of a source and a drain; a first insulating film provided on the first conductive layer; a gate electrode film provided on the first insulating film; a second insulating film provided on the gate electrode film; a gate opening provided so as to penetrate the second insulating film, the gate electrode film and the first insulating film to expose a part of the first conductive layer; a recess provided in the surface of the first conductive layer just below the gate opening; a gate insulator provided on the side surface of the gate opening and having a projecting shape at a portion between the first insulating film and the recess; a second conductive layer buried in the recess and in a bottom of the gate opening so as to be in contact with the gate insulator.Type: GrantFiled: October 9, 2008Date of Patent: August 3, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
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Patent number: 7732891Abstract: A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.Type: GrantFiled: June 3, 2008Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Yoshiaki Fukuzumi, Masaru Kito, Yasuyuki Matsuoka
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Publication number: 20100096682Abstract: A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.Type: ApplicationFiled: September 9, 2009Publication date: April 22, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Akihiro Nitayama, Hideaki Aochi, Hitoshi Ito, Yasuyuki Matsuoka
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Publication number: 20100038699Abstract: A stacked body is formed on a silicon substrate by stacking a plurality of insulating films and a plurality of electrode films alternately and through-holes are formed to extend in the stacking direction. Next, gaps are formed between the electrode films using etching the insulating films via the through-holes. Charge storage layers are formed along side faces of the through-holes and inner faces of the gaps, and silicon pillars are filled into the through-holes. Thereby, a nonvolatile semiconductor memory device is manufactured.Type: ApplicationFiled: August 17, 2009Publication date: February 18, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Yasuyuki Matsuoka
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Publication number: 20100013049Abstract: A first multilayer body is formed by alternately layering dielectric films and electrode films on a substrate. Then, an end portion of the first multilayer body is processed into a staircase shape, and a first interlayer dielectric film is formed around the first multilayer body. Next, a plurality of contact holes having a diameter decreasing downward are formed in the first interlayer dielectric film so that the contact holes reach respective end portions of the electrode films. Then, a sacrificial material is buried in the contact holes. Next, a second multilayer body is formed immediately above the first multilayer body, and a second interlayer dielectric film is formed around the second multilayer body. Thereafter, a plurality of contact holes having a diameter decreasing downward are formed in the second interlayer dielectric film to communicate with the respective contact holes formed in the first interlayer dielectric film.Type: ApplicationFiled: July 17, 2009Publication date: January 21, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Yoshiaki Fukuzumi, Masaru Kito, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Yasuyuki Matsuoka
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Publication number: 20100006922Abstract: The invention provides a nonvolatile semiconductor memory device comprising a plurality of memory strings each including a plurality of electrically programmable memory cells connected in series. The memory string includes a semiconductor pillar, an insulator formed around the circumference of the semiconductor pillar, and first through nth electrodes to be turned into gate electrodes (n denotes a natural number equal to 2 or more) formed around the circumference of the insulator. It also includes interlayer electrodes formed in regions between the first through nth electrodes around the circumference of the insulator.Type: ApplicationFiled: July 8, 2008Publication date: January 14, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuyuki MATSUOKA, Yoshiaki Fukuzumi, Hideaki Aochi
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Publication number: 20090294844Abstract: A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyasu TANAKA, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Yoshiaki Fukuzumi, Masaru Kito, Yasuyuki Matsuoka
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Publication number: 20090267135Abstract: A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction.Type: ApplicationFiled: March 20, 2009Publication date: October 29, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyasu Tanaka, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Hideaki Aochi, Megumi Ishiduki, Yasuyuki Matsuoka
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Publication number: 20090242967Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.Type: ApplicationFiled: March 13, 2009Publication date: October 1, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Ryota KATSUMATA, Masaru Kito, Hiroyasu Tanaka, Masaru Kidoh, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
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Publication number: 20090230462Abstract: Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction.Type: ApplicationFiled: February 26, 2009Publication date: September 17, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Masaru Kidoh, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
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Publication number: 20090230458Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a columnar semiconductor layer extending in a direction perpendicular to a substrate; a plurality of conductive layers formed at a sidewall of the columnar semiconductor layer via memory layers; and interlayer insulation layers formed above of below the conductive layers. A sidewall of the conductive layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes larger at lower position thereof than at upper position thereof. While, a sidewall of the interlayer insulation layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes smaller at lower position thereof than at upper position thereof.Type: ApplicationFiled: February 25, 2009Publication date: September 17, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Megumi ISHIDUKI, Hideaki Aochi, Ryota Katsumata, Hiroyasu Tanaka, Masaru Kidoh, Masaru Kito, Yoshiaki Fukuzumi, Yosuke Komori, Yasuyuki Matsuoka
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Publication number: 20090230459Abstract: A non-volatile semiconductor memory device includes a memory string which is electrically rewritable and includes a plurality of memory cells connected in series. The memory string includes a plurality of first conductive layers which are extended parallel to a substrate and laminated; a first semiconductor layer which is formed so as to pass through the plurality of the first conductive layers; and an electric charge accumulation layer which is formed between the first conductive layer and the first semiconductor layer and is configured so as to be able to accumulate electric charge. The first conductive layer is configured by material smaller in work function than P+-type polysilicon.Type: ApplicationFiled: March 2, 2009Publication date: September 17, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Masaru KITO, Ryota KATSUMATA, Hiroyasu TANAKA, Masaru KIDOH, Yoshiaki FUKUZUMI, Hideaki AOCHI, Yasuyuki MATSUOKA
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Publication number: 20090224309Abstract: A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall insulating layer on a side wall facing the first hole; forming a sacrificing layer so that the sacrificing layer infills the first hole; forming a second conductive layer on an upper layer of the sacrificing layer so that the second conductive layer is sandwiched by the second insulating layer in an up-down direction; forming a second hole on a position which matches with the first hole so that the second hole penetrates the second insulating layer and the second conductive layer; forming a second side wall insulating layer on a side wall facing the second hole; removing the sacrificing layer after the formation of the second side wall insulating layer; and forming a semiconductor layer so thatType: ApplicationFiled: February 20, 2009Publication date: September 10, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Yasuyuki Matsuoka
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Publication number: 20090212350Abstract: A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.Type: ApplicationFiled: February 20, 2009Publication date: August 27, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Masaru KIDOH, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Akihiro Nitayama, Hitoshi Ito, Yasuyuki Matsuoka
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Publication number: 20090179257Abstract: A non-volatile semiconductor memory device includes a first columnar semiconductor layer and a plurality of first conductive layers formed such that a charge storage layer for storing charges is sandwiched between the first conductive layers and the first columnar semiconductor layer. Also, the non-volatile semiconductor memory device includes a second columnar semiconductor layer and a second conductive layer formed such that an insulating layer is sandwiched between the second conductive layer and the second columnar semiconductor layer, the second conductive layer being repeatedly provided in a line form by providing a certain interval in a first direction perpendicular to a laminating direction. A first sidewall conductive layer being in contact with the second conductive layer and extending in the first direction is formed on a sidewall along a longitudinal direction of the second conductive layer.Type: ApplicationFiled: December 29, 2008Publication date: July 16, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yosuke Komori, Masaru Kito, Megumi Ishiduki, Ryota Katsumata, Hiroyasu Tanaka, Masaru Kidoh, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
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Patent number: 7558141Abstract: A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function, second dummy transistors formed above said memory cell transistors, and second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.Type: GrantFiled: December 13, 2007Date of Patent: July 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Masaru Kito, Hideaki Aochi, Yoshiaki Fukuzumi, Yasuyuki Matsuoka
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Publication number: 20090146206Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate and having a first hollow extending downward from its upper end; a first insulation layer formed in contact with the outer wall of the first columnar semiconductor layer; a second insulation layer formed on the inner wall of the first columnar semiconductor layer so as to leave the first hollow; and a plurality of first conductive layers formed to sandwich the first insulation layer with the first columnar semiconductor layer and functioning as control electrodes of the memory cells.Type: ApplicationFiled: November 28, 2008Publication date: June 11, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka