Patents by Inventor Yen-Cheng Liu
Yen-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230086723Abstract: In an embodiment, a processor may include an execution engine to execute a plurality of instructions, a memory to store a tagged data structure comprising a plurality of entries, and an eviction circuit. The eviction circuit may be to: generate a pseudo-random number responsive to an eviction request for the tagged data structure; in response to a determination that the pseudo-random number is outside of a valid eviction range for the plurality of entries, generate an alternative identifier by rotating through the valid eviction range, the valid eviction range comprising a range of numbers that are valid to identify victim entries of the tagged data structure; and evict a victim entry from the tagged data structure, the victim entry associated with the alternative identifier. Other embodiments are described and claimed.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Yongmei Zhang, Yedidya Hilewitz, Yen-Cheng Liu
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Publication number: 20230091205Abstract: Methods and apparatus relating to memory side prefetch architecture for improved memory bandwidth are described. In an embodiment, logic circuitry transmits a Direct Memory Controller Prefetch (DMCP) request to cause a prefetch of data from memory. A memory controller receives the DMCP request and issues a plurality of read operations to the memory in response to the DMCP request. Data read from the memory is stored in a storage structure in response to the plurality of read operations. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Applicant: Intel CorporationInventors: Adrian Moga, Ugonna Echeruo, Eduard Roytman, Krishnakanth Sistla, Joseph Nuzman, Brinda Ganesh, Meenakshisundaram Chinthamani, Yen-Cheng Liu, Sai Prashanth Muralidhara, Vivek Kozhikkottu, Hanna Alam, Narasimha Sridhar Srirangam
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Patent number: 11604730Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.Type: GrantFiled: July 27, 2020Date of Patent: March 14, 2023Assignee: Intel CorporationInventors: Rahul Pal, Philip Abraham, Ajaya Durg, Bahaa Fahim, Yen-Cheng Liu, Sanilkumar Mm
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Patent number: 11591211Abstract: A method of manufacturing a semiconductive structure includes receiving a first substrate; disposing an interconnection layer on the first substrate; forming a plurality of conductors over the interconnection layer; filing gaps between the plurality of conductors with a film; forming a barrier layer over the film; removing the barrier layer; and partially removing the film to expose a portion of the interconnection and leave a portion of the interconnection layer covered by the film.Type: GrantFiled: October 7, 2019Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yen-Cheng Liu, Cheng-Yu Hsieh, Shang-Ying Tsai, Kuei-Sung Chang
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Patent number: 11586579Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.Type: GrantFiled: October 28, 2021Date of Patent: February 21, 2023Assignee: Intel CorporationInventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z. Chrysos, John R. Ayers, Dheeraj R. Subbareddy
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Patent number: 11537520Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.Type: GrantFiled: October 5, 2021Date of Patent: December 27, 2022Assignee: Intel CorporationInventors: Doddaballapur N. Jayasimha, Samantika S. Sury, Christopher J. Hughes, Jonas Svennebring, Yen-Cheng Liu, Stephen R. Van Doren, David A. Koufaty
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Patent number: 11513957Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.Type: GrantFiled: September 21, 2020Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Ren Wang, Andrew J. Herdrich, Yen-cheng Liu, Herbert H. Hum, Jong Soo Park, Christopher J. Hughes, Namakkal N. Venkatesan, Adrian C. Moga, Aamer Jaleel, Zeshan A. Chishti, Mesut A. Ergin, Jr-shian Tsai, Alexander W. Min, Tsung-yuan C. Tai, Christian Maciocco, Rajesh Sankaran
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Patent number: 11500636Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.Type: GrantFiled: February 24, 2020Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Christopher J. Hughes, Joseph Nuzman, Jonas Svennebring, Doddaballapur N. Jayasimha, Samantika S. Sury, David A. Koufaty, Niall D. McDonnell, Yen-Cheng Liu, Stephen R. Van Doren, Stephen J. Robinson
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Publication number: 20220261002Abstract: The described positional awareness techniques employing sensory data gathering and analysis hardware with reference to specific example implementations implement improvements in the use of sensors, techniques and hardware design that can enable specific embodiments to find new area to cover by a robot encountering an unexpected obstacle traversing an area in which the robot is performing an area coverage task. The sensory data are gathered from an operational camera and one or more auxiliary sensors.Type: ApplicationFiled: April 25, 2022Publication date: August 18, 2022Applicant: Trifo, Inc.Inventors: Zhe ZHANG, Weikai LI, Qingyu CHEN, Yen-Cheng LIU
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Patent number: 11314262Abstract: The described positional awareness techniques employing sensory data gathering and analysis hardware with reference to specific example implementations implement improvements in the use of sensors, techniques and hardware design that can enable specific embodiments to find new area to cover by a robot encountering an unexpected obstacle traversing an area in which the robot is performing an area coverage task. The sensory data are gathered from an operational camera and one or more auxiliary sensors.Type: GrantFiled: February 21, 2020Date of Patent: April 26, 2022Assignee: Trifo, Inc.Inventors: Zhe Zhang, Weikai Li, Qingyu Chen, Yen-Cheng Liu
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Publication number: 20220114122Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Applicant: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Patent number: 11294852Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.Type: GrantFiled: June 30, 2020Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z. Chrysos, John R. Ayers, Dheeraj R. Subbareddy
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Patent number: 11294850Abstract: In one embodiment, a system on chip includes: a plurality of intellectual property (IP) agents formed on a semiconductor die; a mesh interconnect formed on the semiconductor die to couple the plurality of IP agents, and a plurality of mesh stops each to couple one or more of the plurality of IP agents to the mesh interconnect. The mesh interconnect may be formed of a plurality of rows each having one of a plurality of horizontal interconnects and a plurality of columns each having one of a plurality of vertical interconnects;, where at least one of the plurality of rows includes an asymmetrical number of mesh stops. Other embodiments are described and claimed.Type: GrantFiled: March 29, 2019Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Brinda Ganesh, Yen-Cheng Liu, Swadesh Choudhary, Tejpal Singh, Pradeep Prabhakaran, Monam Agarwal
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Publication number: 20220091983Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.Type: ApplicationFiled: October 5, 2021Publication date: March 24, 2022Inventors: Doddaballapur N. Jayasimha, Samantika S. Sury, Christopher J. Hughes, Jonas Svennebring, Yen-Cheng Liu, Stephen R. Van Doren, David A. Koufaty
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Patent number: 11269793Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.Type: GrantFiled: July 23, 2020Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Patent number: 11256657Abstract: In one embodiment, an apparatus includes an interconnect to couple a plurality of processing circuits. The interconnect may include a pipe stage circuit coupled between a first processing circuit and a second processing circuit. This pipe stage circuit may include: a pipe stage component having a first input to receive a signal via the interconnect and a first output to output the signal; and a selection circuit having a first input to receive the signal from the first output of the pipe stage component and a second input to receive the signal via a bypass path, where the selection circuit is dynamically controllable to output the signal received from the first output of the pipe stage component or the signal received via the bypass path. Other embodiments are described and claimed.Type: GrantFiled: March 26, 2019Date of Patent: February 22, 2022Assignee: Intel CorporationInventors: Tejpal Singh, Yedidya Hilewitz, Ankush Varma, Yen-Cheng Liu, Krishnakanth V. Sistla, Jeffrey Chamberlain
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Publication number: 20220050805Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.Type: ApplicationFiled: October 28, 2021Publication date: February 17, 2022Inventors: NEVINE NASSIF, YEN-CHENG LIU, KRISHNAKANTH V. SISTLA, GERALD PASDAST, SIVA SOUMYA EACHEMPATI, TEJPAL SINGH, ANKUSH VARMA, MAHESH K. KUMASHIKAR, SRIKANTH NIMMAGADDA, CARLETON L. MOLNAR, VEDARAMAN GEETHA, JEFFREY D. CHAMBERLAIN, WILLIAM R. HALLECK, GEORGE Z. CHRYSOS, JOHN R. AYERS, DHEERAJ R. SUBBAREDDY
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Patent number: 11144108Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.Type: GrantFiled: September 30, 2016Date of Patent: October 12, 2021Assignee: INTEL CORPORATIONInventors: Yen-Cheng Liu, P. Keong Or, Krishnakanth V. Sistla, Ganapati Srinivasa
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Patent number: 11138112Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.Type: GrantFiled: April 11, 2019Date of Patent: October 5, 2021Assignee: Intel CorporationInventors: Doddaballapur N. Jayasimha, Samantika S. Sury, Christopher J. Hughes, Jonas Svennebring, Yen-Cheng Liu, Stephen R. Van Doren, David A. Koufaty
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Publication number: 20210224190Abstract: Examples described herein relate to programming a memory rule for a home agent, wherein the programming a memory rule for a home agent comprises: receiving at least one memory rule programming and based on a cluster associated with the home agent, configuring a memory rule register using a memory rule programming from among the at least one memory rule programming. In some examples, receiving at least one memory rule programming includes receiving a first memory rule programming and receiving a second memory rule programming. In some examples, a mask is applied to reject the first memory rule programming; and applying the mask to accept the second memory rule programming and program the memory rule for the home agent.Type: ApplicationFiled: April 6, 2021Publication date: July 22, 2021Inventors: Vinit MATHEW ABRAHAM, Yen-Cheng LIU