Abstract: The described positional awareness techniques employing sensory data gathering and analysis hardware with reference to specific example implementations implement improvements in the use of sensors, techniques and hardware design that can enable specific embodiments to find new area to cover by a robot encountering an unexpected obstacle traversing an area in which the robot is performing an area coverage task. The sensory data are gathered from an operational camera and one or more auxiliary sensors.

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.

Abstract: The described positional awareness techniques employing sensory data gathering and analysis hardware with reference to specific example implementations implement improvements in the use of sensors, techniques and hardware design that can enable specific embodiments to find new area to cover by a robot performing an area coverage task of an unexplored area. The sensory data are gathered from an operational camera and one or more auxiliary sensors.

Abstract: A method of manufacturing a semiconductive structure includes receiving a first substrate; disposing an interconnection layer on the first substrate; forming a plurality of conductors over the interconnection layer; filing gaps between the plurality of conductors with a film; forming a barrier layer over the film; removing the barrier layer; and partially removing the film to expose a portion of the interconnection and leave a portion of the interconnection layer covered by the film.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.

Abstract: A method of new radio physical broadcast channel (NR-PBCH) bit mapping is proposed to improve for NR-PBCH decoding performance under Polar codes. NR-PBCH carries 32 information bits and 24 CRC bits. Specifically, NR-PBCH uses 512-bit Polar codes to carry total 56 data bits. Different Polar code bit channels have different channel reliability. As a general rule, the most reliable Polar code bit channels are used for the 56 data bits. In accordance with a novel aspect, within the 32 NR-PBCH information bits, some of the information bits that can be known to the decoders under certain conditions and therefore are placed at the least reliable Polar code bit positions. As a result, by mapping the NR-PBCH data bits properly at the input bit positions of Polar codes, the NR-PBCH decoding performance is improved when the known bits a priori can be exploited.

Abstract: A semiconductive structure includes a first substrate comprising an interconnection layer and a first conductor protruding from the interconnection layer, a second substrate comprising a second conductor bonded with the first conductor, a first cavity between and sealed by the first substrate and the second substrate and the first cavity has a first cavity pressure, a second cavity between and sealed by the first substrate and the second substrate and the second cavity has a second cavity pressure, a first surface of the interconnection layer is a sidewall of the first cavity, wherein the first cavity pressure is less than the second cavity pressure.

Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

Abstract: Buffered interconnects for highly scalable on-die fabric and associated methods and apparatus. A plurality of nodes on a die are interconnected via an on-die fabric. The nodes and fabric are configured to implement forwarding of credited messages from source nodes to destination nodes using forwarding paths partitioned into a plurality of segments, wherein separate credit loops are implemented for each segment. Under one fabric configuration implementing an approach called multi-level crediting, the nodes are configured in a two-dimensional grid and messages are forwarded using vertical and horizontal segments, wherein a first segment is between a source node and a turn node in the same row or column and the second segment is between the turn node and a destination node. Under another approach called buffered mesh, buffering and credit management facilities are provided at each node and adjacent nodes are configured to implement credit loops for forwarding messages between the nodes.

Abstract: In one embodiment, a system on chip includes: a plurality of intellectual property (IP) agents formed on a semiconductor die; a mesh interconnect formed on the semiconductor die to couple the plurality of IP agents, and a plurality of mesh stops each to couple one or more of the plurality of IP agents to the mesh interconnect. The mesh interconnect may be formed of a plurality of rows each having one of a plurality of horizontal interconnects and a plurality of columns each having one of a plurality of vertical interconnects;, where at least one of the plurality of rows includes an asymmetrical number of mesh stops. Other embodiments are described and claimed.

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.

Abstract: A starvation mode is entered and a particular dependency of a first request in a retry queue is identified. The particular dependency is determined to be acquired and the first request is retried based on acquisition of the particular dependency.

Abstract: Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.

Abstract: A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

Abstract: A semiconductive structure includes a first substrate including a first surface and a second surface opposite to the first surface, a second substrate disposed over the first surface and including a first device and a second device, a first capping structure disposed over the second substrate, and including a via extending through the first capping structure to the second device, a first cavity surrounding the first device and defined by the first capping structure and the first substrate, a second cavity surrounding the second device and defined by the first capping structure and the first substrate, and a second capping structure disposed over the first capping structure and covering the via, wherein the second cavity and the via are sealed by the second capping structure.

Abstract: Aspects of the disclosure provide a method and device performing input bit allocation that includes receiving broadcasting information bits, generating timing related bits for the broadcasting information bits, and selecting a portion of the generated timing related bits. The method and device can further include allocating each of the selected timing related bits to selected input bits of an encoder, so that each of the selected timing related bits is allocated to an input bit of the encoder corresponding to an available bit channel of the encoder where the selected inputs bits of the encoder correspond to encoded bits that are located in a front portion of the encoded bits.

Abstract: A method for adaptively performing a set of data transfer processes in a multi-core processor is described. The method may include receiving, by a shared cache from a first core cache, a first request for a cache line; determining, by the shared cache in response to receipt of the first request, whether the cache line is a widely-shared cache line or a single-producer-single-consumer cache line; and performing, by the first core cache and a second core cache, a three-hop data transfer process in response to determining that the cache line is a single-producer-single-consumer cache line, wherein the three-hop data transfer process transfers the cache line directly from the second core cache to the first core cache.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.