Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

Abstract: Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.

Abstract: A semiconductive structure includes a first substrate comprising an interconnection layer and a first conductor protruding from the interconnection layer, a second substrate comprising a second conductor bonded with the first conductor, a first cavity between and sealed by the first substrate and the second substrate and the first cavity has a first cavity pressure, a second cavity between and sealed by the first substrate and the second substrate and the second cavity has a second cavity pressure, a first surface of the interconnection layer is a sidewall of the first cavity, wherein the first cavity pressure is less than the second cavity pressure.

Abstract: A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

Abstract: A method of new radio physical broadcast channel (NR-PBCH) bit mapping is proposed to improve for NR-PBCH decoding performance under Polar codes. NR-PBCH carries 32 information bits and 24 CRC bits. Specifically, NR-PBCH uses 512-bit Polar codes to carry total 56 data bits. Different Polar code bit channels have different channel reliability. As a general rule, the most reliable Polar code bit channels are used for the 56 data bits. In accordance with a novel aspect, within the 32 NR-PBCH information bits, some of the information bits that can be known to the decoders under certain conditions and therefore are placed at the least reliable Polar code bit positions. As a result, by mapping the NR-PBCH data bits properly at the input bit positions of Polar codes, the NR-PBCH decoding performance is improved when the known bits a priori can be exploited.

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Abstract: In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.

Abstract: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.

Abstract: A speculative read request is received from a host device over a buffered memory access link for data associated with a particular address. A read request is sent for the data to a memory device. The data is received from the memory device in response to the read request and the received data is sent to the host device as a response to a demand read request received subsequent to the speculative read request.

Abstract: Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.

Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

Abstract: A semiconductor device includes a first wafer and a second wafer. The first wafer has a top portion. The second wafer is disposed on the top portion of the first wafer, wherein the second wafer has a bottom portion bonded on the top portion of the first wafer, and a non-bonded area of the bottom portion has a width smaller than 0.5 mm. The bottom portion of the second wafer has a size smaller than or equal to that of the top portion of the first wafer. In some embodiments, the top portion of the first wafer has first rounded corners, and the bottom portion of the second wafer has second corners. A cross-sectional view of each of the second rounded corners has a radius smaller than that of each of first rounded corners. In some embodiments, the bottom portion of the second wafer has right angle corners.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.

Abstract: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.

Abstract: An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC.

Abstract: Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.

Abstract: Apparatus and methods implementing a Remote Snoop Filter (“RSF”) for reducing unnecessary snoops to one or more Field Programmable Gate Arrays (“FPGAs”) in a hardware system by tracking the address and state of each cache line cached in the FPGA's cache. The apparatus include one or more processors, one or more FPGAs, and a system memory. Each processor further comprises a Caching and Home Agent (“CHA”), an L3 or Last Level Cache (“LLC”), and one or more cores wherein each core contains a core cache. The CHA implements and manages an RSF which tracks the address and state of each cache line stored in the one or more FPGAs. The hit/miss result from an RSF lookup is used by the CHA to determine whether or not to filter snoops to the FPGAs. A cache line miss in the RSF indicates that the requested cache line is not in any of the FPGAs and thus no snoop to the FPGA should be issued. This ensures that the FPGAs are generally not snooped unless necessary.

Abstract: A speculative read request is received from a host device over a buffered memory access link for data associated with a particular address. A read request is sent for the data to a memory device. The data is received from the memory device in response to the read request and the received data is sent to the host device as a response to a demand read request received subsequent to the speculative read request.

Abstract: Efficient algorithms for estimating LSFCs with no aid of SSFCs by taking advantage of the channel hardening effect and large spatial samples available to a massive MIMO base station (BS) are proposed. The LSFC estimates are of low computational complexity and require relatively small training overhead. In the uplink direction, mobile stations (MSs) transmit orthogonal uplink pilots for the serving BS to estimate LSFCs. In the downlink direction, the BS transmits either pilot signal or data signal intended to the MSs that have already established time and frequency synchronization. The proposed uplink and downlink LSFC estimators are unbiased and asymptotically optimal as the number of BS antennas tends to infinity.