Patents by Inventor Yen-Hao Chen

Yen-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090058560
    Abstract: A power plane includes a first circuit region and a second circuit region. The length of the first circuit region or second circuit region is related to the noise frequency to be filtered out. The width of the first circuit region can be wider or narrower than the width of the second circuit region. While manufacturing the power plane, a predetermined length is decided according to the resonance frequency of an original power plane, then the proposed power plane is formed with the first circuit region and the second circuit region of a predetermined length, and making the width of the first circuit region wider or narrower than the width of the second circuit region, such that the noises with the resonance frequency can be mitigated.
    Type: Application
    Filed: August 31, 2007
    Publication date: March 5, 2009
    Inventor: Yen-Hao Chen
  • Patent number: 7449641
    Abstract: A high-speed signal transmission structure having parallel disposed and serially connected vias is disclosed. The structure is applicable to a multi-layered circuit board such as a high-speed digital circuit board for forming a high-speed signal transmission circuit on the high-speed digital circuit board. The structure includes a pair of parallel disposed and serially connected vias for connecting an upper conductive circuit installed on an upper layer of the multi-layered circuit board and a lower conductive circuit installed on a lower layer of the multi-layered circuit board. Compared with the prior art, an open stub formed by the remaining portion of the vias has become shorter, thereby reducing a resonance effect affecting the quality of signal transmission.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: November 11, 2008
    Assignee: Inventec Corporation
    Inventor: Yen-Hao Chen
  • Publication number: 20080158840
    Abstract: A DC power plane structure applied in multi-layer circuit board is provided. The DC power plane structure includes a first circuit area for receiving a DC power, a noise filter with one end electrically connected to a DC power output end of the first circuit area, and a second circuit area which is electrically isolated from the first circuit area. The second circuit area has a band gap structure, and the DC power input end of the band gap structure is electrically connected to the other end of the noise filter for inhibiting high-frequency noise generated between layers of the multi-layer circuit board.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Applicant: INVENTEC CORPORATION
    Inventors: Yen-Hao Chen, Chun-Yu Lai
  • Publication number: 20080072204
    Abstract: A layout design of a multilayer printed circuit board (PCB) is provided, which makes use of partial electromagnetic band gap (EBG) structure to constitute a power layer or a ground layer. The EBG structure is mainly used on the linear transmission path from the port of the first integrated circuit to the port of the second integrated circuit on the power layer or the ground layer, so as to overcome the problems concerning self-impedance and transfer-impedance easily occurred in the conventional complete EBG structure.
    Type: Application
    Filed: September 19, 2006
    Publication date: March 20, 2008
    Applicant: INVENTEC CORPORATION
    Inventor: Yen-Hao Chen
  • Publication number: 20080048798
    Abstract: A transmission line used in in-circuit testing point applies the impedance matching concept to optimize the line length and line width of a part of the transmission line where connects to the in-circuit testing point in order to exhibit the high impedance inductance property to approach the impedance matching for the design frequency. Therefore, the discontinuous effect caused by the low impedance property of the capacitive point can be improved.
    Type: Application
    Filed: August 23, 2006
    Publication date: February 28, 2008
    Applicant: INVENTEC CORPORATION
    Inventors: Chih-Ming Yang, Yen-Hao Chen
  • Publication number: 20080042775
    Abstract: A design for a transmission line on an over split plane structure is provided, which optimizes the line length and line width of the line segment of transmission line part connected to the over split plane structure by using a concept of impedance match, such that this part of line segment behaves with a capacitive low impedance characteristic, achieving the impedance match at a designed frequency point, and thereby eliminating a discontinuous effect caused by a high impedance characteristic of the electrical property of transmission line on the over split plane structure.
    Type: Application
    Filed: August 17, 2006
    Publication date: February 21, 2008
    Applicant: INVENTEC CORPORATION
    Inventors: Chih-Ming Yang, Yen-Hao Chen
  • Publication number: 20080017411
    Abstract: A high-speed signal transmission structure having parallel disposed and serially connected vias is disclosed. The structure is applicable to a multi-layered circuit board such as a high-speed digital circuit board for forming a high-speed signal transmission circuit on the high-speed digital circuit board. The structure includes a pair of parallel disposed and serially connected vias for connecting an upper conductive circuit installed on an upper layer of the multi-layered circuit board and a lower conductive circuit installed on a lower layer of the multi-layered circuit board. Compared with the prior art, an open stub formed by the remaining portion of the vias has become shorter, thereby reducing a resonance effect affecting the quality of signal transmission.
    Type: Application
    Filed: July 24, 2006
    Publication date: January 24, 2008
    Applicant: Inventec Corporation
    Inventor: Yen-Hao Chen
  • Publication number: 20070132527
    Abstract: A suppression method for suppressing a via stub effect of a substrate is disclosed. The suppression method is applicable to a substrate having a via, a first conductive line and a second conductive line connected through the via to the first conductive line. The suppression method includes changing a first width of a first conductive segment of the first conductive line connected to the via, and changing a second width of a second conductive segment of the second conductive line connected to the via, so as to change impedances of the first conductive line and the second conductive line to match with a stub impedance of the via, reduce a parasite impedance of the via stub, reach an impedance match at a designed frequency point, and improve an integrity of a signal after traveling from the first conductive line, the via and the second conductive line.
    Type: Application
    Filed: March 31, 2006
    Publication date: June 14, 2007
    Inventor: Yen-Hao Chen
  • Publication number: 20050071798
    Abstract: A power supply layout for an integrated circuit has a plurality of power pads, a plurality of ground pads, a plurality of first-type conductive wires directly connected to the power pad, a plurality of second-type conductive wires directly connected to the ground pad, and a core circuit electrically connected to the first-type and the second-type conductive wires for acquiring the operational power. The integrated circuit is made of a plurality of metal layers, wherein the first-type conductive wire and the second-type conductive wire are positioned at different metal layers. The power pad is positioned at the same metal layer as the first-type conductive wire, while the ground pad is positioned at the same metal layer as the second-type conductive wire.
    Type: Application
    Filed: November 25, 2003
    Publication date: March 31, 2005
    Applicant: GOYATEK TECHNOLOGY INC.
    Inventors: Ching-Yao Chung, Nai-Yin Sung, Yen-Hao Chen
  • Patent number: 6571368
    Abstract: The present invention includes a method and device useful for decoding a Reed-Solomon (N, K) encoded message of m-bit symbols and corresponding syndromes, where N<=2m−1 and N−K=2t. Systolic calculation cells are used, organized to minimize complexity and computation time. Aspects of the invention include designs for syndrome calculation, division of polynomials over a Galois field, applying Euclid's algorithm, partitioning calculation cell arrays to reduce storage requirements, complexity and computation time, and evaluating an error location and polynomial and an error evaluator polynomial.
    Type: Grant
    Filed: February 2, 2000
    Date of Patent: May 27, 2003
    Assignee: Macronix International Co., Ltd.
    Inventor: Yen-Hao Chen
  • Patent number: 5936747
    Abstract: The present invention includes a housing for providing space to hold elements of the scanning system, a document holder is used for holding a document, which can be separated from the scanning system. Further, the document holder consists of a first cover and a second cover. One end of the first cover is connected to one end of the second cover via a pair of pins. The document holder can be pivotally opened for feeding the document into the document holder. A plate having an opening is connected to the housing. The opening is used to provide a path for feeding the document holder into the scanning system. An image capture device is set in the scanning system for capturing the image of the document. A pair of tracks respectively are attached on the inner side walls of the housing for holding the document holder. Document holder rejecting means is utilized for rejecting the document holder.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: August 10, 1999
    Assignee: Mustek Systems Inc.
    Inventors: John Lin, Yen-Hao Chen