Patents by Inventor Yen-Hung Lin

Yen-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10956643
    Abstract: A method includes: accessing a design data of an integrated circuit (IC), wherein the design data includes a transistor layer and a plurality of metal layers over the transistor layer; assigning a bin size for each of the metal layers based on layout properties of the respective metal layers, wherein the bin sizes are progressively larger from a bottom layer to a top layer of the metal layers; performing resource planning on the transistor layer and each of the metal layers according to the assigned bin sizes of the respective metal layers; and updating the design data according to the resource planning. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Patent number: 10877370
    Abstract: A method for mitigating extreme ultraviolet (EUV) mask defects is disclosed. The method includes the steps of providing a wafer blank, identifying a first plurality of defects on the wafer blank, providing an EUV mask design on top of the wafer blank, identifying non-critical blocks with corresponding stretchable zones on the EUV mask design, overlapping the EUV blank with the EUV mask design, identifying a second plurality of defects, the second plurality of defects are solved, identifying a third plurality of defects, the third plurality of defects are not solved, adjusting the relative locations of the EUV mask design and the EUV blank to solve at least one of the third plurality of defects, and adjusting the locations of at least one of the non-critical blocks within corresponding stretchable zones to solve at least one of the third plurality of defects.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Lin Yang, Chin-Chang Hsu, Yen-Hung Lin, Chung-Hsing Wang, Wen-Ju Yang
  • Patent number: 10878157
    Abstract: An integrated circuit that includes a first row having a first height, with a first cell in the first row that has the first height. The integrated circuit further includes a second row having a second height, where the first height is not an integer multiple of the second height. A second cell is in the second row that has the second height.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 29, 2020
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Patent number: 10818515
    Abstract: The present disclosure provides an electronic package and a method for fabricating the same. A protective layer is formed on a carrier of the electronic component. The electronic component and the protective layer are covered by a covering layer. A through hole is formed in the covering layer and extends through the protective layer, such that a portion of a surface of the carrier is exposed to the through hole. A conductive structure is disposed in the through hole and electrically connected with the carrier. Through the formation of the protective layer, the buffering effect of the protective layer can prevent the laser from directly burning through the covering layer and the protective layer to avoid damages to the carrier.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 27, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Wei Yeh, Yen-Hung Lin, Chih-Yi Liao, Chih-Hsien Chiu
  • Publication number: 20200265180
    Abstract: A method includes: accessing a design data of an integrated circuit (IC), wherein the design data includes a transistor layer and a plurality of metal layers over the transistor layer; assigning a bin size for each of the metal layers based on layout properties of the respective metal layers, wherein the bin sizes are progressively larger from a bottom layer to a top layer of the metal layers; performing resource planning on the transistor layer and each of the metal layers according to the assigned bin sizes of the respective metal layers; and updating the design data according to the resource planning. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Inventors: YEN-HUNG LIN, CHUNG-HSING WANG, YUAN-TE HOU
  • Patent number: 10732725
    Abstract: A method of interactive display based on gesture recognition includes determining a plurality of gestures corresponding to a plurality of images, interpreting a predetermined combination of gestures among the plurality of gestures as a command, and displaying a scene in response to the command.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 4, 2020
    Assignee: XRSpace CO., LTD.
    Inventors: Peter Chou, Feng-Seng Chu, Yen-Hung Lin, Shih-Hao Ke, Jui-Chieh Chen
  • Publication number: 20200226316
    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung LIN, Chung-Hsing Wang, Yuan-Te Hou
  • Patent number: 10678342
    Abstract: A method of virtual user interface interaction based on gesture recognition comprises detecting two hands in a plurality of images, recognizing each hand's gesture, projecting a virtual user interface on an open gesture hand when one hand is recognized with a point gesture and the other hand is recognized with an open gesture, tracking an index fingertip of the point gesture hand, determining whether the index fingertip of the point gesture hand is close to the open gesture hand within a predefined rule, interpreting a movement of the index fingertip of the point gesture hand as a click command when the index fingertip of the point gesture hand is close to the open gesture hand within the predefined rule, and in response to the click command, generating image data with a character object of the virtual user interface object.
    Type: Grant
    Filed: October 21, 2018
    Date of Patent: June 9, 2020
    Assignee: XRSpace CO., LTD.
    Inventors: Peter Chou, Feng-Seng Chu, Yen-Hung Lin, Shih-Hao Ke, Jui-Chieh Chen
  • Patent number: 10671788
    Abstract: A method includes accessing a design data of an integrated circuit (IC), the design data including a plurality of layers. For each of the layers, the method performs: assigning a bin size of the respective layer based on a layout property of the respective layer; and performing a bin-based feature allocation according to the assigned bin size. The method also includes updating the design data according to the bin-based feature allocation. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Patent number: 10664092
    Abstract: A portable electronic device, an operating method for the same, and a non-transitory computer readable recording medium are provided. The portable electronic device includes a body, a touch display screen and an edge sensor. The touch display screen is disposed on the body. The edge sensor is disposed adjacent to an edge of the body. The operating method includes the following step. When an event is generated according to a first action sensed by the edge sensor, a touch function of a region of the touch display screen or the whole touch display screen is disabled.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 26, 2020
    Assignee: HTC Corporation
    Inventors: Chia-Yao Lin, Yen-Hung Lin, Shih-Lung Lin, Chia-Chu Ho, Hsuan-Yi Lee, Kuan-Wei Li, Jian-Shuen Chen, Yu-Hung Chen, Chun-Hung Hsieh, Pin-Yu Huang
  • Patent number: 10643986
    Abstract: A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 10642949
    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Publication number: 20200134124
    Abstract: A method (of generating a layout diagram) includes generating a cell, representing at least part of a circuit in a semiconductor device, which is arranged at least in part according to second tracks of the M_2nd level (M_2nd tracks), and first tracks of the M_1st level (M_1st tracks). The generating the cell includes: selecting, based on a chosen site for the cell in the layout diagram, one of the M_2nd tracks; generating a first M_2nd pin pattern representing an output pin of the circuit; arranging a long axis of the first pin pattern substantially along the selected M_2nd track; generating second, third, fourth and fifth M_1st pin patterns representing corresponding input pins of the circuit; and arranging long axes of the second to fifth pin patterns substantially along corresponding ones of the M_1st tracks.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 30, 2020
    Inventors: Pin-Dai SUE, Chin-Chou LIU, Sheng-Hsiung CHEN, Fong-Yuan CHANG, Lee-Chung LU, Yen-Hung LIN, Li-Chun TIEN, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU
  • Publication number: 20200125783
    Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Yen-Hung LIN, Yuan-Te HOU, Chung-Hsing WANG
  • Publication number: 20200125176
    Abstract: A method of virtual user interface interaction based on gesture recognition comprises detecting two hands in a plurality of images, recognizing each hand's gesture, projecting a virtual user interface on an open gesture hand when one hand is recognized with a point gesture and the other hand is recognized with an open gesture, tracking an index fingertip of the point gesture hand, determining whether the index fingertip of the point gesture hand is close to the open gesture hand within a predefined rule, interpreting a movement of the index fingertip of the point gesture hand as a click command when the index fingertip of the point gesture hand is close to the open gesture hand within the predefined rule, and in response to the click command, generating image data with a character object of the virtual user interface object.
    Type: Application
    Filed: October 21, 2018
    Publication date: April 23, 2020
    Inventors: Peter Chou, Feng-Seng Chu, Yen-Hung Lin, Shih-Hao Ke, Jui-Chieh Chen
  • Publication number: 20200097091
    Abstract: A method of interactive display based on gesture recognition includes determining a plurality of gestures corresponding to a plurality of images, interpreting a predetermined combination of gestures among the plurality of gestures as a command, and displaying a scene in response to the command.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Peter Chou, Feng-Seng Chu, Yen-Hung Lin, Shih-Hao Ke, Jui-Chieh Chen
  • Publication number: 20200090952
    Abstract: The present disclosure provides an electronic package and a method for fabricating the same. A protective layer is formed on a carrier of the electronic component. The electronic component and the protective layer are covered by a covering layer. A through hole is formed in the covering layer and extends through the protective layer, such that a portion of a surface of the carrier is exposed to the through hole. A conductive structure is disposed in the through hole and electrically connected with the carrier. Through the formation of the protective layer, the buffering effect of the protective layer can prevent the laser from directly burning through the covering layer and the protective layer to avoid damages to the carrier.
    Type: Application
    Filed: November 20, 2018
    Publication date: March 19, 2020
    Inventors: Yu-Wei Yeh, Yen-Hung Lin, Chih-Yi Liao, Chih-Hsien Chiu
  • Patent number: D889464
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 7, 2020
    Assignee: XRSPACE CO., LTD.
    Inventors: Chieh-Kai Wang, Yen-Hung Lin
  • Patent number: D900095
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 27, 2020
    Assignee: XRSPACE CO., LTD.
    Inventors: Chieh-Kai Wang, Yen-Hung Lin
  • Patent number: D900096
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 27, 2020
    Assignee: XRSPACE CO., LTD.
    Inventors: Chieh-Kai Wang, Yen-Hung Lin