Patents by Inventor Yen-Hung Lin

Yen-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10067668
    Abstract: A portable electronic device, an operating method for the same, and a non-transitory computer readable recording medium are provided. The portable electronic device includes a body and an edge sensor disposed adjacent to an edge of the body. The operating method includes the following step. When a plugging-in event or a plugging-out event of a peripheral device is detected by the portable electronic device, a squeezing event sensed by the edge sensor is ignored. The squeezing event may be generated when a squeeze action sensed by the edge sensor occurs during a first time period. The plugging-in event or the plugging-out event may occur during the first time period. Alternatively, the squeeze action may begin within a second time period after the plugging-in event or the plugging-out event occurs.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: September 4, 2018
    Assignee: HTC CORPORATION
    Inventors: Chia-Yao Lin, Yen-Hung Lin, Shih-Lung Lin, Chia-Chu Ho, Hsuan-Yi Lee, Kuan-Wei Li, Jian-Shuen Chen, Yu-Hung Chen, Chun-Hung Hsieh, Pin-Yu Huang
  • Publication number: 20180210993
    Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes forming a first partition by selecting at least one in-boundary PG cell from the group of PG cells, adding at least one out-boundary PG cell from the group of PG cells into the first partition, forming a second partition by selecting the remaining in-boundary PG cells and the remaining out-boundary PG cells in the group of PG cells, calculating the total area of the in-boundary PG cells in the first partition, calculating the total area of the out-boundary PG cells in the first partition, calculating the total area of the in-boundary PG cells in the second partition, calculating the total area of the out-boundary PG cells in the second partition, and calculating the difference between the total areas of in-boundary PG cells in the first partition and the out-boundary PG cells in the first partition.
    Type: Application
    Filed: October 3, 2017
    Publication date: July 26, 2018
    Inventors: Yen-Hung LIN, Yuan-Te HOU, Chung-Hsing WANG
  • Publication number: 20180165406
    Abstract: A method includes operations below. A layout of a circuit is converted to a first conflict graph. A first vertex and a second vertex in the first conflict graph are adjusted based on first data indicating a color patterns assignment for the circuit, in order to generate a second conflict graph, in which the first vertex indicates a first pattern in the layout, and the second vertex indicates a second pattern in the layout. According to the second conflict graph, a first color pattern is assigned to both of the first pattern and the second pattern, or the first color pattern is assigned to the first pattern and a second color pattern is assigned to the second pattern, in order to generate second data for fabricating the circuit.
    Type: Application
    Filed: May 15, 2017
    Publication date: June 14, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Hung LIN, Yuan-Te HOU, Chin-Chang HSU
  • Publication number: 20180096967
    Abstract: An electronic package structure is provided, which includes: a plurality of first and second electronic components disposed on opposite sides of a carrier; a blocking member formed between adjacent two of the first electronic components; an encapsulant encapsulating the first and second electronic components and the blocking member; and a shielding element formed on the encapsulant to improve the electromagnetic shielding effect. The present disclosure further provides a method for fabricating the electronic package structure.
    Type: Application
    Filed: February 17, 2017
    Publication date: April 5, 2018
    Inventors: Wen-Jung Tsai, Cheng-Kai Chang, Yen-Hung Lin, Hsin-Lung Chung
  • Publication number: 20180074692
    Abstract: A portable electronic device, an operating method for the same, and a non-transitory computer readable recording medium are provided. The portable electronic device includes a body and an edge sensor disposed adjacent to an edge of the body. The operating method includes the following step. When a plugging-in event or a plugging-out event of a peripheral device is detected by the portable electronic device, a squeezing event sensed by the edge sensor is ignored. The squeezing event may be generated when a squeeze action sensed by the edge sensor occurs during a first time period. The plugging-in event or the plugging-out event may occur during the first time period. Alternatively, the squeeze action may begin within a second time period after the plugging-in event or the plugging-out event occurs.
    Type: Application
    Filed: May 15, 2017
    Publication date: March 15, 2018
    Applicant: HTC Corporation
    Inventors: Chia-Yao LIN, Yen-Hung LIN, Shih-Lung LIN, Chia-Chu HO, Hsuan-Yi LEE, Kuan-Wei LI, Jian-Shuen CHEN, Yu-Hung CHEN, Chun-Hung HSIEH, Pin-Yu HUANG
  • Publication number: 20180074645
    Abstract: A portable electronic device, an operating method for the same, and a non-transitory computer readable recording medium are provided. The portable electronic device includes a body, a touch display screen and an edge sensor. The touch display screen is disposed on the body. The edge sensor is disposed adjacent to an edge of the body. The operating method includes the following step. When an event is generated according to a first action sensed by the edge sensor, a touch function of a region of the touch display screen or the whole touch display screen is disabled.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 15, 2018
    Applicant: HTC Corporation
    Inventors: Chia-Yao LIN, Yen-Hung LIN, Shih-Lung LIN, Chia-Chu HO, Hsuan-Yi LEE, Kuan-Wei LI, Jian-Shuen CHEN, Yu-Hung CHEN, Chun-Hung HSIEH, Pin-Yu HUANG
  • Publication number: 20180068046
    Abstract: A method of designing a layout includes assigning a first color group to a plurality of first routing tracks. The method includes assigning a second color group to a plurality of second routing tracks. A first routing track is between adjacent second routing tracks. The method includes assigning a color from the first color group to each default conductive element along each first routing track. A color of a first default conductive element along each first routing track is different from a color of an adjacent default conductive element along a same first routing track. The method includes assigning a color from the second color group to each default conductive element along each second routing track. A color of a first default conductive element along each second routing track is different from a color of an adjacent default conductive element along a same second routing track.
    Type: Application
    Filed: September 8, 2016
    Publication date: March 8, 2018
    Inventors: Yen-Hung LIN, Chung-Hsing WANG, Yuan-Te HOU
  • Publication number: 20180047716
    Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.
    Type: Application
    Filed: October 23, 2017
    Publication date: February 15, 2018
    Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 9864413
    Abstract: An accessory suitable for an electronic device is provided. The electronic device has a display area. The accessory includes a coupling portion and a cover portion. The coupling portion is suitable to be coupled to the electronic device. The cover portion is connected to the coupling portion and is suitable for covering the display area of the electronic device. The cover portion has a plurality of light-transmitting areas, and the light-transmitting areas are arranged on the display area in an array. An image generated by the display area is projected out of the cover portion through the light-transmitting areas. Moreover, an electronic assembly containing the electronic device and the accessory is also provided. Furthermore, a control method is also provided for controlling the electronic assembly. A method is also provided for forming an accessory.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: January 9, 2018
    Assignee: HTC Corporation
    Inventors: Yen-Hung Lin, Chien-Wei Hsieh, Chun-Ta Huang, Hung-Chuan Wen, Michael Ross Massucco
  • Patent number: 9799639
    Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
  • Publication number: 20170286289
    Abstract: A FLASH memory control technique with wear leveling between the different blocks of the FLASH memory. By a controller managing the blocks of a FLASH memory within a data storage device, some of the blocks are pushed into a spare queue waiting to be allocated as data blocks or system blocks. When the number of blocks within the spare queue is lower than a clean threshold and any block within the spare queue has an erase count greater than an overused lower threshold, the controller performs a garbage correction operation with wear leveling between the different blocks.
    Type: Application
    Filed: June 22, 2017
    Publication date: October 5, 2017
    Inventors: Po-Chia CHU, Yen-Hung LIN
  • Publication number: 20170244885
    Abstract: The present invention is to provide a network camera with manually adjustable shooting angle which includes a base fastened on a plane, a main frame having a bottom end connected to the base and a positioning ring disposed on a top end thereof, and a camera device having a structure matching with the inner periphery of the positioning ring so as to be assembled with the main frame integrally and rotatably positioned in the positioning ring. The positioning ring has a plurality of first engagement parts disposed on an inner periphery thereof, and the camera device has at least one second engagement part which is disposed on a peripheral edge thereof and can be engaged with one of the first engagement parts, so as to make sure that the camera device can be manually adjusted to a normal shooting angle for capturing image having a normal view angle.
    Type: Application
    Filed: April 22, 2016
    Publication date: August 24, 2017
    Applicant: D-Link Corporation
    Inventor: Yen-Hung LIN
  • Patent number: 9733806
    Abstract: An electronic device and a user interface operating method thereof. The electronic device comprises an input unit and a processing unit. The input unit detects an input from a user. The processing unit adjusts a home screen from a first display location to a second display location according to the input.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: August 15, 2017
    Assignee: HTC CORPORATION
    Inventors: Yen-Hung Lin, Lan-Lan Ma, Yu-Yen Wen
  • Patent number: 9720820
    Abstract: A FLASH memory control technique with wear leveling between the different blocks of the FLASH memory. By a controller managing the blocks of a FLASH memory within a data storage device, some of the blocks are pushed into a spare queue waiting to be allocated as data blocks or system blocks. When the number of blocks within the spare queue is lower than a clean threshold and any block within the spare queue has an erase count greater than an overused lower threshold, the controller performs a garbage correction operation with wear leveling between the different blocks.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: August 1, 2017
    Assignee: SILICON MOTION, INC.
    Inventors: Po-Chia Chu, Yen-Hung Lin
  • Publication number: 20170169154
    Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.
    Type: Application
    Filed: December 11, 2015
    Publication date: June 15, 2017
    Inventors: Yen-Hung LIN, Chung-Hsing WANG, Chin-Chou LIU, Chi-Wei HU
  • Patent number: 9659141
    Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Cheng-I Huang, Chin-Chang Hsu, Hung Lung Lin
  • Patent number: 9659133
    Abstract: A method is performed at least in part by at least one processor. In the method, a plurality of circuit elements are placed in a layout for a semiconductor device, the plurality of circuit elements having a plurality of pins. A layer assignment is generated to assign a plurality of interconnections to corresponding conductive layers of the semiconductor device, the plurality of interconnections connecting corresponding pairs of pins among the plurality of pins. The plurality of interconnections is routed in the layout in accordance with the layer assignment.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hung Lin, Chi Wei Hu, Yuan-Te Hou, Chung-Hsing Wang, Chin-Chou Liu
  • Patent number: 9642546
    Abstract: The present invention proposes a relaxation state evaluation system and method and a computer program product thereof. The method comprises steps: measuring ECG data of a user; analyzing the ECG data to generate a first, second, third and fourth parameters, wherein the first parameter is the short-scale entropy slope of the user before cardiovascular disease treatment (CVDT); the second parameter is the difference of the post-CVDT and pre-CVDT mean RR intervals; the third parameter is the logarithm of the variance of the pre-CVDT high frequency NN intervals; the fourth parameter is the logarithm of the ratio of the variances of the pre-CVDT low frequency and high frequency NN intervals; working out an evaluation index, which is a function of the abovementioned parameters; and evaluating the relaxation state of the user, wherein the user is determined to be in a relaxation state if the evaluation index is over a threshold.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: May 9, 2017
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Hung-Chih Chiu, Yi-Lwun Ho, Yen-Hung Lin, Hsi-Pin Ma, Tzung-Dau Wang, Chun-Chieh Chan, Hung-Chun Lu
  • Patent number: D785613
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: May 2, 2017
    Assignee: HTC Corporation
    Inventors: Yen-Hung Lin, Michael Ross Massucco
  • Patent number: D801947
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 7, 2017
    Assignee: Google Inc.
    Inventors: Rachael Elizabeth Gordon, Alberto Villarreal Bello, Robert Edward Mangum, Max Ken Yoshimoto, Yen Hung Lin, Yi Hsin Lin