Patents by Inventor Yi Chou

Yi Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140128528
    Abstract: The disclosure provides a white coating composition, and a device employing a coating made of the composition. The white coating composition includes 20-55 parts by weight of silicon dioxide particles, 40-75 parts by weight of inorganic material, and 5-40 parts by weight of silsequioxane, wherein the silsequioxane is prepared from monomers comprising a first monomer represented by the Formula (I) and a second monomer represented by the Formula (II) wherein, R1 is independently the same or different methyl or ethyl, and R2 is independently the same or different C1-6 alkyl.
    Type: Application
    Filed: September 10, 2013
    Publication date: May 8, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tsung-Yi CHOU, Chyi-Ming LEU
  • Publication number: 20140119058
    Abstract: A power voltage conversion system for a controller integrated circuit includes a DC-to-DC converter and a controller IC. The DC-to-DC converter receivers an external DC voltage and the DC-to-DC converter at least has an inductance element and a switch element. The inductance element has at least one first winding and one second winding and the first winding is connected to the second winding in series. The controller IC is electrically connected to the inductance element and the switch element. The external DC voltage is converted into at least one power voltage according to a turn ratio between the first winding and the second winding, thus supplying power to the controller IC to control the switch element.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: Chicony Power Technology Co., Ltd.
    Inventors: Keng-Yi CHOU, Chia-Chieh LIN
  • Patent number: 8691706
    Abstract: System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Fang Wen Tsai, Kuang-Wei Cheng, Jiann Sheng Chang, Yi Chou Lai, Jiung Wu
  • Publication number: 20140071637
    Abstract: A touch panel includes a first substrate and a first composite material conductive layer. The first composite material conductive layer has a first multilayer structure. The first multilayer structure includes a first refraction index compensating layer, a second refraction index compensating layer, and a first metal conductive layer. The first refraction index compensating layer, the first metal conductive layer, and the second compensation layer are stacked on the first substrate, and an equivalent refraction index of the first composite material conductive layer is substantially between a refraction index of the first substrate and 1.1 times the refraction index of the first substrate.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 13, 2014
    Applicants: WINTEK CORPORATION, Wintek (China) Technology Ltd.
    Inventors: Chang-Hsuan Hsu, Wen-Chun Wang, Cheng-Yi Chou, Heng-Yi Chang, Chien-Chung Chen, Ching-Fu Hsu, Chong-Wei Li, Ting-Yu Chang, Kuo-Chang Su
  • Patent number: 8664689
    Abstract: A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: March 4, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsiang-Lan Lung, Erh-Kun Lai, Yen-Hao Shih, Yi-Chou Chen, Shih-Hung Chen
  • Publication number: 20140035034
    Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.
    Type: Application
    Filed: October 3, 2013
    Publication date: February 6, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
  • Publication number: 20140018512
    Abstract: A reactant composition includes: a diol component; a diacid-derived component; and a modifier represented by the following formula (I): wherein R1, R2, and R3 independently represent H or a methyl group, and at least one of R1, R2, and R3 is a methyl group. A polyester made from the reactant composition is also disclosed.
    Type: Application
    Filed: May 30, 2013
    Publication date: January 16, 2014
    Applicant: FAR EASTERN NEW CENTURY CORPORATION
    Inventors: Roy Wu, Yi-Hsuan Tang, Hsin-Yi Chou
  • Publication number: 20140010028
    Abstract: A reading method of a memory is provided. The memory has a turn on window. The reading method comprises the following steps. A reading voltage is provided. The reading voltage is shown if the reading voltage is located in the turn on window. The reading voltage is updated by moving a predetermined distance if the reading voltage is not located in the turn on window. The predetermined distance is cut by half before the step of updating the reading voltage is performed again.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Tsung-Yi Chou
  • Publication number: 20130342891
    Abstract: An electrowetting display device includes a lower substrate, an upper substrate, a medium layer, a lower electrode, an upper electrode, and a molecular chain layer. The medium layer is disposed between the lower substrate and the upper substrate. The medium layer includes a first medium and a second medium separated from each other. The first medium is a light transmission medium, and the second medium is a light-shielding medium. The lower electrode is disposed between the medium layer and the lower substrate. The molecular chain layer is disposed between the medium layer and the lower electrode. The molecular chain layer includes molecular chains. Each molecular chain has a first section and a second section. The first section is used to attract the first medium or repel the second medium. The second section is used to attract the second medium or repel the first medium.
    Type: Application
    Filed: June 26, 2013
    Publication date: December 26, 2013
    Inventors: Chih-Yuan Wang, Cheng-Yi Chen, Cheng-Yi Chou, Tai-Yen Lai, Yu-Hua Wu, Chen-Wei Li
  • Publication number: 20130346673
    Abstract: A method for improving flash memory storage device access is disclosed. The steps of the method comprises requesting to read/write data of logical address by a host; setting up an engine by a CPU; looking up physical address and updating at least one table stored in at least one flash memory by the engine; and reading/writing data from/to the at least one flash memory. Thereby, the engine is accessing the data from each table in parallel to significantly reduce the total operation time.
    Type: Application
    Filed: June 25, 2012
    Publication date: December 26, 2013
    Inventor: Yi-Chou Chen
  • Patent number: 8587058
    Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.
    Type: Grant
    Filed: January 2, 2012
    Date of Patent: November 19, 2013
    Assignee: United Microelectronics Corp.
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen, Ming-Yong Jian
  • Patent number: 8581338
    Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: November 12, 2013
    Assignee: United Microelectronics Corp.
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
  • Patent number: 8573663
    Abstract: A finger-gesticulation hand device includes a base frame representing a metacarpal part of the human hand, and at least three digits mounted on the base frame and appearing to be a thumb and at least two fingers. Each digit has at least two phalange portions respectively linked by two joints which permit a flexing movement of the phalange portions between extended and flexed positions. An actuating cord passes through each digit and is actuated by a solenoid actuator unit to pull the phalange portions of the respective digit to the flexed position. The hand device is simple in construction and capable of making hand gestures in a simple manner.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: November 5, 2013
    Assignee: Precision Machinery Research & Development Center
    Inventors: Rong-Bin Lin, Ying-Lung Lin, Bo-Yi Chou, Che-Hau Wu
  • Publication number: 20130285404
    Abstract: A finger-gesticulation hand device includes a base frame representing a metacarpal part of the human hand, and at least three digits mounted on the base frame and appearing to be a thumb and at least two fingers. Each digit has at least two phalange portions respectively linked by two joints which permit a flexing movement of the phalange portions between extended and flexed positions. An actuating cord passes through each digit and is actuated by a solenoid actuator unit to pull the phalange portions of the respective digit to the flexed position. The hand device is simple in construction and capable of making hand gestures in a simple manner.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: PRECISION MACHINERY RESEARCH & DEVELOPMENT CENTER
    Inventors: Rong-Bin Lin, Ying-Lung Lin, Bo-Yi Chou, Che-Hau Wu
  • Publication number: 20130206568
    Abstract: A touch panel including a first substrate, a second substrate, a first sensing layer, a second sensing layer, and a plurality of spacers is provided. The second substrate is parallel to and opposite to the first substrate in a top-bottom manner. The first sensing layer is disposed on the first substrate and located between the first substrate and the second substrate. The second sensing layer is disposed on the second substrate. The spacers are located between the first sensing layer and the second sensing layer, and the spacers includes a plurality of movable first spacers and a plurality of second spacers fixed on the second substrate, wherein each of the first spacers is surrounded by a portion of the second spacers.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 15, 2013
    Applicants: WINTEK CORPORATION, Dongguan Masstop Liquid Crystal Display Co., Ltd.
    Inventors: Yu-Hua Wu, Cheng-Yi Chou, Chih-Yuan Wang, Ting-Yu Chang, Ching-Fu Hsu, Hsiao-Hui Liao
  • Publication number: 20130199257
    Abstract: A back cover manufacturing method includes providing a striped sheet, bending the striped sheet along a long side of the striped sheet to form a hem, cutting the striped sheet to make the striped sheet have at least one concave portion formed thereon for correspondingly forming a plurality of striped sections, and bending the plurality of striped sections to form a back cover. The back cover is used for being disposed in a backlight module to hold at least one optical component of the backlight module.
    Type: Application
    Filed: April 19, 2012
    Publication date: August 8, 2013
    Inventor: Fang-Yi Chou
  • Publication number: 20130183831
    Abstract: System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.
    Type: Application
    Filed: January 12, 2012
    Publication date: July 18, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Fang Wen Tsai, Kuang-Wei Cheng, Jiann Sheng Chang, Yi Chou Lai, Jiung Wu
  • Patent number: 8482063
    Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 9, 2013
    Assignee: United Microelectronics Corporation
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Wei-Chun Chang, Chun-Yao Lee, Kun-Yi Chou
  • Publication number: 20130168767
    Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.
    Type: Application
    Filed: January 2, 2012
    Publication date: July 4, 2013
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen, Ming-Yong Jian
  • Patent number: 8451085
    Abstract: A co-fired multi-layer stack chip resistor is provided. The co-fired multi-layer stack chip resistor includes a ceramic substrate and a multi-layer stack resistance structure monomer. The ceramic substrate is formed by stacking multiple layers of the ceramic membranes, wherein the ceramic membranes is formed of a bearing membrane and a porcelain slurry with the solvent, the binder and the dispersant. The multi-layer stack resistance structure monomer is stacked on the ceramic substrate, and includes multiple bearing membranes and multiple resistive layers, wherein each resistive layer is formed on the surface of the corresponding bearing membrane, the resistive layers are parallel to each other, and the contiguous resistive layers are stacked with the interval of the predetermined distance along the vertical direction.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: May 28, 2013
    Assignee: Prosperity Dielectrics Co., Ltd.
    Inventors: Yung Cheng Tsai, Ching Jen Tsai, Tung Yi Chou, Hung Chun Wu