Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.

Abstract: A reactant composition includes: a diol component; a diacid-derived component; and a modifier represented by the following formula (I): wherein R1, R2, and R3 independently represent H or a methyl group, and at least one of R1, R2, and R3 is a methyl group. A polyester made from the reactant composition is also disclosed.

Abstract: A reading method of a memory is provided. The memory has a turn on window. The reading method comprises the following steps. A reading voltage is provided. The reading voltage is shown if the reading voltage is located in the turn on window. The reading voltage is updated by moving a predetermined distance if the reading voltage is not located in the turn on window. The predetermined distance is cut by half before the step of updating the reading voltage is performed again.

Abstract: An electrowetting display device includes a lower substrate, an upper substrate, a medium layer, a lower electrode, an upper electrode, and a molecular chain layer. The medium layer is disposed between the lower substrate and the upper substrate. The medium layer includes a first medium and a second medium separated from each other. The first medium is a light transmission medium, and the second medium is a light-shielding medium. The lower electrode is disposed between the medium layer and the lower substrate. The molecular chain layer is disposed between the medium layer and the lower electrode. The molecular chain layer includes molecular chains. Each molecular chain has a first section and a second section. The first section is used to attract the first medium or repel the second medium. The second section is used to attract the second medium or repel the first medium.

Abstract: A method for improving flash memory storage device access is disclosed. The steps of the method comprises requesting to read/write data of logical address by a host; setting up an engine by a CPU; looking up physical address and updating at least one table stored in at least one flash memory by the engine; and reading/writing data from/to the at least one flash memory. Thereby, the engine is accessing the data from each table in parallel to significantly reduce the total operation time.

Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.

Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.

Abstract: A finger-gesticulation hand device includes a base frame representing a metacarpal part of the human hand, and at least three digits mounted on the base frame and appearing to be a thumb and at least two fingers. Each digit has at least two phalange portions respectively linked by two joints which permit a flexing movement of the phalange portions between extended and flexed positions. An actuating cord passes through each digit and is actuated by a solenoid actuator unit to pull the phalange portions of the respective digit to the flexed position. The hand device is simple in construction and capable of making hand gestures in a simple manner.

Abstract: A finger-gesticulation hand device includes a base frame representing a metacarpal part of the human hand, and at least three digits mounted on the base frame and appearing to be a thumb and at least two fingers. Each digit has at least two phalange portions respectively linked by two joints which permit a flexing movement of the phalange portions between extended and flexed positions. An actuating cord passes through each digit and is actuated by a solenoid actuator unit to pull the phalange portions of the respective digit to the flexed position. The hand device is simple in construction and capable of making hand gestures in a simple manner.

Abstract: A touch panel including a first substrate, a second substrate, a first sensing layer, a second sensing layer, and a plurality of spacers is provided. The second substrate is parallel to and opposite to the first substrate in a top-bottom manner. The first sensing layer is disposed on the first substrate and located between the first substrate and the second substrate. The second sensing layer is disposed on the second substrate. The spacers are located between the first sensing layer and the second sensing layer, and the spacers includes a plurality of movable first spacers and a plurality of second spacers fixed on the second substrate, wherein each of the first spacers is surrounded by a portion of the second spacers.

Abstract: A back cover manufacturing method includes providing a striped sheet, bending the striped sheet along a long side of the striped sheet to form a hem, cutting the striped sheet to make the striped sheet have at least one concave portion formed thereon for correspondingly forming a plurality of striped sections, and bending the plurality of striped sections to form a back cover. The back cover is used for being disposed in a backlight module to hold at least one optical component of the backlight module.

Abstract: System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.

Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.

Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.

Abstract: A lateral-diffusion metal-oxide-semiconductor device includes a semiconductor substrate having at least a field oxide layer, a gate having a layout pattern of a racetrack shape formed on the substrate, a common source formed in the semiconductor substrate and enclosed by the gate, and a drain surrounding the gate and formed in the semiconductor substrate. The gate covers a portion of the field oxide layer. The common source includes a first doped region having a first conductive type and a plurality of islanding second doped regions having a second conductive type. The drain includes a third doped region having the first conductive type. The third doped region overlaps a portion of the field oxide layer and having an overlapping area between the third doped region and the field oxide layer.

Abstract: A co-fired multi-layer stack chip resistor is provided. The co-fired multi-layer stack chip resistor includes a ceramic substrate and a multi-layer stack resistance structure monomer. The ceramic substrate is formed by stacking multiple layers of the ceramic membranes, wherein the ceramic membranes is formed of a bearing membrane and a porcelain slurry with the solvent, the binder and the dispersant. The multi-layer stack resistance structure monomer is stacked on the ceramic substrate, and includes multiple bearing membranes and multiple resistive layers, wherein each resistive layer is formed on the surface of the corresponding bearing membrane, the resistive layers are parallel to each other, and the contiguous resistive layers are stacked with the interval of the predetermined distance along the vertical direction.

Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.

Abstract: A co-fired multi-layer stack chip resistor is provided. The co-fired multi-layer stack chip resistor includes a ceramic substrate and a multi-layer stack resistance structure monomer. The ceramic substrate is formed by stacking multiple layers of the ceramic membranes, wherein the ceramic membranes is formed of a bearing membrane and a porcelain slurry with the solvent, the binder and the dispersant. The multi-layer stack resistance structure monomer is stacked on the ceramic substrate, and includes multiple bearing membranes and multiple resistive layers, wherein each resistive layer is formed on the surface of the corresponding bearing membrane, the resistive layers are parallel to each other, and the contiguous resistive layers are stacked with the interval of the predetermined distance along the vertical direction.

Abstract: A hollow toy structure includes at least a first and a second shell portion, which are configured as two three-dimensional concave members with their rims forming two mating joining surfaces, which can be assembled to each other for closing the first shell portion to the second shell portion to form a hollow body. On and along the joining surface of the first shell portion, there is provided at least one annular groove as a first coupling structure, which is located between an outer and an inner surface of the first shell portion; and on and along the joining surface of the second shell portion, there is provided at least one retaining ring as a second coupling structure for complementarily engaging with the annular groove. And, a bonding layer is applied on between the joining surfaces of the first and second shell portions to bond the two shell portions together.

Abstract: A blue phase liquid crystal composition includes a chiral dopant, a positive liquid crystal component and a negative liquid crystal component. The positive liquid crystal component includes at least one positive liquid crystal material, has a positive dielectric anisotropy and has no blue phase properties with respect to the chiral dopant. In addition, the negative liquid crystal component includes at least one negative liquid crystal material, has a negative dielectric anisotropy and has no blue phase properties with respect to the chiral dopant, so that the blue phase liquid crystal composition has a dielectric anisotropy between 0.5 and 14 and a blue phase temperature range larger than 3° C.