Abstract: Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.

Abstract: A memory cell is arranged to enhance the electrical field of the memory element. The memory cell has a metal-oxide memory element, a nonconductive element, and a conductive element. The metal-oxide memory element is in a current path between a first electrode at a first voltage and a second electrode at a second voltage. The nonconductive element is adjacent to the metal-oxide memory element.

Abstract: A phase change device includes a first contact electrode structure a phase change material and a first insulating material between the phase change material and the first contact electrode structure and a second contact electrode in contact with the phase change material. A contact structure formed in the first insulating material between the first contact electrode structure and the phase change material is also included. The contact structure is formed by an insulating material breakdown process. A method of forming a phase change device is also described.

Abstract: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.

Abstract: Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a reset bias arrangement to a memory cell to change the resistance state from the lower resistance state to the higher resistance state. The reset bias arrangement comprises a first voltage pulse. The method further includes applying a set bias arrangement to the memory cell to change the resistance state from the higher resistance state to the lower resistance state. The set bias arrangement comprises a second voltage pulse, the second voltage pulse having a voltage polarity different from that of the first voltage pulse.

Abstract: A power converting apparatus including a power converting unit and a control unit is provided. The power converting unit receives an input voltage and generates an output voltage for a display driving unit according to a control signal. The control unit provides the control signal to the power converting unit, wherein the control unit adjusts the duty cycle or the frequency of the control signal according to an image signal. In addition, a power converting method is also provided.

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode.

Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

Abstract: A compact auto focus lens module includes a piezoelectric actuator, an elastic element, at least two guiding fixtures, and a lens barrel with an optical lens set therein. By elastic force of the elastic element, a friction is generated between the lens barrel and the piezoelectric actuator. While being applied with a voltage, the lens barrel driven by the movement of the piezoelectric actuator moves along the optical axis under the guidance of the guiding fixtures. Due to fewer elements, compact volume, and light weight, the design is applied to a miniature auto focus lens modules so as to achieve effects of fast movement, stable focusing and reduced tilting.

Abstract: An image processing apparatus for deinterlacing and vertical scaling a plurality of initial scan lines includes a control unit, a deinterlacer, a vertical scaler and a buffer. The control unit controls the deinterlacer and the vertical scaler to store parts of the processed scan lines thereof into the buffer according to a scaling ratio factor and a vertical scaling algorithm.

Abstract: A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance.

Abstract: A method of storing data in a multi-level charge-trapping memory array is described. An incidence-of-occurrence (i.e., frequency) analysis is performed on data to be programmed to identify data words combining a high programming voltage with a high frequency of occurrence. Those words are reassigned in order to reduce programming time.

Abstract: A pliable handle for a hand-held device is provided. The handle includes a tubular core member, a deformable outer sheath disposed about the tubular core member, a gel disposed between the tubular core member and the outer sheath, and first and second sealers inserted into respective ends of the tubular core member and sealing the gel between the tubular core member and the outer sheath, wherein a force applied to the outer sheath causes load movement of the gel.

Abstract: A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer; a conductive ion buffer layer between the ion-supplying layer and the memory layer, and which allows diffusion therethrough of said ions; and a second electrode electrically coupled to the ion-supplying layer. Circuitry is coupled to the device to apply bias voltages to the first and second electrodes to induce creation and destruction of conducting bridges including the first metal element in the memory layer. The ion buffer layer can improve retention of the conducting bridge by reducing the likelihood that the first metallic element will be absorbed into the ion supplying layer.

Abstract: A method of efficiently programming charge-trapping memory cells includes sense amplifiers being dynamically connected to cells to be programmed, by switching bit lines. The method increases a number of cells that can be programmed simultaneously, such that an optimal use of sense amplifier resources is obtained.

Abstract: Various aspect are directed to a memory device or memory cell with a metal-oxide memory element arranged in electrical series along a current path between at least a first electrode, a metal-oxide memory element adjacent to the first electrode, and a second electrode. The first electrode comprises an electrode material having a first work function. The metal-oxide memory element comprises a metal-oxide material having a second work function. The first work function is greater than the second work function. Thermionic emission characterizes the current through this memory.

Abstract: An error assessment method for a test stimulus signal of an analog to digital converter is disclosed. The method provides random uniform-distribution test signals for an analog to digital converter (ADC), derives the piecewise linearity relationship between the input signals and the output signals of the ADC and thus develops an error assessment method for a test stimulus signal of the ADC. The method is able to reduce the computational complexity but still accurate and effective, and thereby provides correct information of the test stimulus signals for testing the ADC to improve its correctness.

Abstract: Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.

Abstract: A multi-level, phase change memory cell has first and second thermal isolation materials having different thermal conductivity properties situated in heat-conducting relation to first and second boundaries of the phase change material. Accordingly, when an electrical current is applied to raise the temperature of the memory material, heat is drawn away from the memory material asymmetrically along a line orthogonal to electric field lines between the electrodes.