Abstract: A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits.

Abstract: An embedded structure of circuit board is provided. The embedded structure of the present invention includes a dielectric layer, a pad opening disposed in the dielectric layer, and a via disposed in the pad opening and in the dielectric layer, wherein the outer surface of the dielectric layer has a substantially even surface.

Abstract: An embedded structure of circuit board is provided. The embedded structure of the present invention includes a dielectric layer, a pad opening disposed in the dielectric layer, and a via disposed in the pad opening and in the dielectric layer, wherein the outer surface of the dielectric layer has a substantially even surface.

Abstract: A fabricating process of a structure with an embedded circuit is described as follows. Firstly, a substrate having an upper surface and a lower surface opposite to the upper surface is provided. Afterward, a dielectric layer is formed on the upper surface of the substrate. Next, a plating-resistant layer is formed on the dielectric layer. Then, the plating-resistant layer and the dielectric layer are patterned for forming an recess pattern on the dielectric layer. Subsequently, a conductive base layer is formed in the recess pattern by using a chemical method, and the plating-resistant layer is exposed by the conductive base layer. After that, the plating-resistant layer is removed.

Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.

Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.

Abstract: Various embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the nonvolatile memory apparatus may include: a host interface; a memory controller coupled to the host interface; and a memory area including a plurality of chips controlled by the memory controller. The memory controller may be configured to assign logical addresses to the plurality of chips to form a plurality of virtual logical groups, set a plurality of threshold values and a plurality of scan ranges depending on the total erase count (TEC) of each logical group, and perform wear-leveling in stages.

Abstract: A storage system is provided. The storage system comprises a storage media, a storage controller and a host. The storage controller is connected to the storage media. The host is connected to the storage controller, and performs a physical resource management algorithm for managing a physical resource of the storage media, so as to output at least a media operation command to the storage controller. The storage controller performs the media operation command to manage the storage media. A storage management method is also provided.

Abstract: The disclosure provides a unit with a sound isolation/vibration isolation structure, an array employing the same, and a method for fabricating the same. The unit with a sound isolation/vibration isolation structure includes: a hollow frame surrounding an inside space; a film disposed within the inside space, vertically contacting an inside wall of the hollow frame; and a body mass disposed on a top surface of the film. Particularly, the horizontal area of the inside space is larger than the area of the top surface of the film.

Abstract: A composition with catalyst particles for making a circuit pattern is provided. The composition includes an insulation material and a plurality of catalyst particles. The catalyst particles are distributed in the insulation material and not made of metal. When the composition is bathed in a chemical plating solution, a redox reaction takes place between some of the catalyst particles and the chemical plating solution so as to deposit a conductive pattern on the composition.

Abstract: A cutter shifting mechanism includes a main body having a longitudinal cylinder casing and a shaft is located in the longitudinal cylinder casing. An arm is connected to a lower end of the shaft so as to be connected with cutters. A longitudinal pushing device is connected to a top end of the shaft and a gear is rotatably mounted to the shaft. The gear is movable along a longitudinal axis of the shaft. A threaded rod is engaged with the gear and connected with a latitude pushing device. Each of the longitudinal and latitude pushing devices includes a pneumatic cylinder. The mechanism includes simple structure and can be manufactured at low cost. The pneumatic cylinders accurately operate the parts of the mechanism.

Abstract: The invention provides an anther-specific expression promoter in plant, wherein said promoter is a promoter of Oncidium aureusidin synthase gene OgAS1, and has a sequence as SEQ ID No: 3. The invention provides further a gene expression cassette that comprised a promoter having a DNA sequence as SEQ ID No: 3, and a polynucleotide that encode an open reading frame and is linked to the 3? end of said promoter, wherein said promoter can activate the transcription of said polynucleotide in an organism containing said gene expression cassette. The invention provides also a gene expression vector that contains a promoter having DNA sequence as SEQ ID No: 3. The invention provides further a process for producing a transgenic plant or part of organ, tissue or cell of said transgenic plant containing the above-described gene expression cassette.

Abstract: An embedded structure of circuit board is provided. The embedded structure of the present invention includes a dielectric layer, a pad opening disposed in the dielectric layer, and a via disposed in the pad opening and in the dielectric layer, wherein the outer surface of the dielectric layer has a substantially even surface.

Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.

Abstract: The invention provides an anther-specific expression promoter in plant, wherein said promoter is a promoter of Oncidium aureusidin synthase gene OgAS1, and has a sequence as SEQ ID No: 3. The invention provides further a gene expression cassette that comprised a promoter having a DNA sequence as SEQ ID No: 3, and a polynucleotide that encode an open reading frame and is linked to the 3? end of said promoter, wherein said promoter can activate the transcription of said polynucleotide in an organism containing said gene expression cassette. The invention provides also a gene expression vector that contains a promoter having DNA sequence as SEQ ID No: 3. The invention provides further a process for producing a transgenic plant or part of organ, tissue or cell of said transgenic plant containing the above-described gene expression cassette.

Abstract: A fabricating process of a structure with an embedded circuit is described as follows. Firstly, a substrate having an upper surface and a lower surface opposite to the upper surface is provided. Afterward, a dielectric layer is formed on the upper surface of the substrate. Next, a plating-resistant layer is formed on the dielectric layer. Then, the plating-resistant layer and the dielectric layer are patterned for forming an recess pattern on the dielectric layer. Subsequently, a conductive base layer is formed in the recess pattern by using a chemical method, and the plating-resistant layer is exposed by the conductive base layer. After that, the plating-resistant layer is removed.

Abstract: A method for making an optical device comprises steps of: 1) Providing a substrate, a polymerizable liquid crystal material having a plurality of liquid crystal molecules, and a mold having rows of trenches; 2) Imprinting the polymerizable liquid crystal material on said substrate by the mold; 3) Proceeding a cross-linking process to cure the liquid crystal material so as to have long axes of the liquid crystal molecules be aligned along the rows of trenches. The optical device made from the present method conforms to an A-plate type retardation plate. Moreover, the optical device is capable of aligning liquid crystal molecules adjacent to it.

Abstract: A cutter shifting mechanism includes a main body having a longitudinal cylinder casing and a shaft is located in the longitudinal cylinder casing. An arm is connected to a lower end of the shaft so as to be connected with cutters. A longitudinal pushing device is connected to a top end of the shaft and a gear is rotatably mounted to the shaft. The gear is movable along a longitudinal axis of the shaft. A threaded rod is engaged with the gear and connected with a latitude pushing device. Each of the longitudinal and latitude pushing devices includes a pneumatic cylinder. The mechanism includes simple structure and can be manufactured at low cost. The pneumatic cylinders accurately operate the parts of the mechanism.

Abstract: A wear-leveling method for managing flash memory is provided, including an access process to consult a translation table when accessing a data block in the data region, and a reconstruction process to reconstruct the translation table when powering on the flash memory. The translation table is defined to include a plurality of entries, and each entry includes a physical address field and an enduring counter field. The logical address of a data block is used as input to map to the entry in the translation table. The access process, further including a read process and an erase/program process, maps the logical address to the physical address, and uses the enduring counter to determine whether an update is required to avoid the disturbance. The reconstruct process uses the information stored in the spare data region to reconstruct the translation table for the access process to consult during flash memory accesses.

Abstract: A smart storage device that can be either used in conjunction with a conventional storage device or integrated into a conventional storage device to become a smart storage device is disclosed. The smart storage device of the present invention includes a transmission interface, a processor, a control interface, a storage medium, an input interface, an input device, a response interface, and a response device. The processor further includes a memory, a data transmission and medium control module, and a monitor, analysis and response (MAR) module. The MAR module is for monitoring and analyzing the operation requests and responding accordingly. When used in conjunction with a conventional storage device, the external smart storage device includes a host-end transmission interface, a processor, a device-end transmission interface, an input device, an input device, a response interface, and a response device.