Abstract: A manufacturing method of a semiconductor structure includes the following steps. A substrate is provided, and an epitaxial structure is formed on the substrate. A first dielectric layer covering the epitaxial structure and the substrate is formed. A patterned hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the patterned hard mask layer and the first dielectric layer. A patterned photoresist layer is formed on the second dielectric layer. A dry etching process is performed with the pattern hard mask layer and the patterned photoresist layer as masks. The dry etching process forms a contact opening in the first dielectric layer, and the contact opening exposes at least a part of the epitaxial structure. A wet etching process is performed after the dry etching process, and the wet etching process removes the patterned hard mask layer and the second dielectric layer together.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.

Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.

Abstract: According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first region and a second region; a first contact plug on the first region, and a second contact plug on the second region. Preferably, the first contact plug includes a first interfacial layer having a first conductive type and a first work function metal layer having the first conductive type on the first interfacial layer, and the second contact plug includes a second interfacial layer having a second conductive type and a second work function metal layer having the second conductive type on the second interfacial layer.

Abstract: A character adjustment method is used for adjusting the character so as to output the character to a second pixel matrix of an output device. The character is designed in a first pixel matrix. The method includes determining a constant, an upper density limit and a lower density limit according to at least one feature value of the output device; performing an interpolation calculation for obtaining a variation parameter according to a density of the character in the first pixel matrix, the constant, the upper density limit and the lower density limit; adjusting the character according to the variation parameter; and outputting the adjusted character to the second pixel matrix by the output device.

Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.

Abstract: The present invention provides a method for regulating aldehyde dehydrogenase 1 (ALDH1) comprises administering all-trans retinoic acid to a subject. Further, the present invention also provides a method for treating solid malignancy comprises administering all-trans retinoic acid to a subject, providing a new choice in current cancer treatment.

Abstract: An intelligent control faucet includes a faucet that includes a manual operation valve, an intelligent control module, a water egress tube, a cold water ingress tube, a hot water ingress tube, and a magnetic reed detection device. The water egress tube, the cold water ingress tube, and the hot water ingress tube are connected to the manual operation valve. The intelligent control module is connected, in a series manner, to the water egress tube. The magnetic reed detection device is mounted to the water egress tube and is connected through a feeding cable or directly to the intelligent control module. Water flow can be established or cut off through pulling the water egress tube so that the use is made easy.

Abstract: Semiconductor devices and manufacturing method thereof are disclosed. The semiconductor device includes a substrate, a device layer, first and second conductive layers, first and second vias, and a MIM capacitor structure. The substrate includes active and passive regions. The device layer is in the active region. The first conductive layer is over the device layer. The second conductive layer is over the first conductive layer, wherein the first conductive layer is disposed between the device layer and the second conductive layer. The first via electrically connects the first and the second conductive layers. The MIM capacitor structure is between the first and the second conductive layers and in the passive region, and includes first and second electrodes and a capacitor dielectric layer therebetween. The capacitor dielectric layer includes Group IIIA-metal oxide or nitride. The second via electrically connects the second conductive layer and one of the first and second electrodes.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a lead frame including a die paddle. A supporting bar connects to the die paddle, extending in an outward direction from the die paddle. At least two power leads are separated from the die paddle and the supporting bar, having first terminals close to the die paddle and second terminals extending outward from the die paddle. A power bar connects to the at least two power leads, having a supporting portion. A molding material encapsulates the lead frame leaving the supporting portion exposed.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first fin-shaped structure and a second fin-shaped structure on the substrate; forming a first epitaxial layer on the first fin-shaped structure and a second epitaxial layer on the second fin-shaped structure; and forming a cap layer on the first epitaxial layer and the second epitaxial layer. Preferably, a distance between the first epitaxial layer and the second epitaxial layer is between twice the thickness of the cap layer and four times the thickness of the cap layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Abstract: A semiconductor device and manufacturing method thereof are provided in the present invention. A second opening is formed corresponding to a gate structure after a step of forming a first opening corresponding to an epitaxial layer. After the step of forming the second opening, a pre-amorphization implantation process is performed to form an amorphous region in the epitaxial layer, and the influence of the process of forming the second opening on the amorphous region may be avoided. The semiconductor device formed by the manufacturing method of the present invention includes a contact structure and an alloy layer. The contact structure is disposed in the second opening for being electrically connected to a metal gate. The alloy layer is disposed on the metal gate and disposed between the metal gate and the contact structure. The alloy layer includes an alloy of the material of the metal gate.

Abstract: An intelligent control faucet includes a faucet that includes a manual operation valve, an intelligent control module, a water egress tube, a cold water ingress tube, a hot water ingress tube, and a magnetic reed detection device. The water egress tube, the cold water ingress tube, and the hot water ingress tube are connected to the manual operation valve. The intelligent control module is connected, in a series manner, to the water egress tube. The magnetic reed detection device is mounted to the water egress tube and is connected through a feeding cable or directly to the intelligent control module. Water flow can be established or cut off through pulling the water egress tube so that the use is made easy.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.