Patents by Inventor Yi Jing

Yi Jing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method
    Patent number: 10770359
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Tsung-Hsi Yang, Ming-Hua Yu
  • Method for determining the position of mobile node and related communication system, road side unit, and vehicle thereof
    Patent number: 10754003
    Abstract: A method for determining the position of a mobile node applied to a roadside unit (RSU) is provided. The RSU and a plurality of mobile nodes form a communication network of a road. The method includes the steps of: obtaining, by, via at least one sensor, first road information, wherein the first road information provides absolute position distribution information associated with the mobile nodes; receiving, by a communication device, second road information from a first mobile node of the mobile nodes, wherein the second road information provides relative position distribution information associated with the first mobile node and second mobile nodes adjacent to the first mobile node; and determining, by a comparison device, the position of the first mobile node on the road according to the first road information and the second road information.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: August 25, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Po-Chun Kang, Tzu-Hsiang Su, Kuo-Huang Hsu, Pei-Chuan Tsai, Yi-Jing Lee
  • Structure and method for semiconductor device
    Patent number: 10727229
    Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; and two fins in a first region of the semiconductor device extending from the substrate and through the isolation structure. Each of the two fins has a channel region and two source/drain (S/D) regions sandwiching the channel region. The semiconductor device further includes a gate stack over the isolation structure and engaging the channel regions of the two fins; and four S/D features over the S/D regions of the two fins. Each of the four S/D features includes a lower portion and an upper portion over the lower portion. Each of the lower portions of the four S/D features has a cross-sectional profile that is wider at its bottom than at its top. The upper portions of the four S/D features merge into two merged S/D features with one on each side of the gate stack.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu
  • Semiconductor device and manufacturing method of a semiconductor device
    Patent number: 10714487
    Abstract: A semiconductor device includes a transistor, an isolation structure, and a fin sidewall structure. The transistor includes a fin extending from a substrate and an epitaxy structure grown on the fin. The isolation structure is above the substrate. The fin sidewall structure is above the isolation structure and is on a sidewall of the epitaxy structure. A method for manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu, Kun-Mu Li
  • Virtual machine (VM)-to-VM flow control using congestion status messages for overlay networks
    Patent number: 10698718
    Abstract: In one embodiment, a system includes a processing circuit and logic integrated with and/or executable by the processing circuit that causes the processing circuit to receive a congestion notification message from a first virtual switch of a first server indicating that a first virtual machine (VM) hosted by the first server is overloaded. The logic also causes the processing circuit to advertise a congestion status of the first VM in a congestion status message to one or more virtual switches in a network in response to receiving the congestion notification message. Moreover, the logic causes the processing circuit to cause all virtual switches in the network except for the first virtual switch to stop sending traffic destined for the first VM while the first VM is overloaded without restricting sending traffic that is destined for other VMs hosted by the first server.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Liang Rong, Gang Tang, Zi Jin Tao, Ming Shuang Xian, Yi Jing Zhu
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES
    Publication number: 20200176581
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.
    Type: Application
    Filed: November 25, 2019
    Publication date: June 4, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing LEE, Chih-Shin KO, Clement Hsingjen WANN
  • FinFET semiconductor device with germanium diffusion over silicon fins
    Patent number: 10665674
    Abstract: A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor material, replacing a first portion of at least one of the fins with a second semiconductor material, and distributing the second semiconductor material from the first portion to a second portion of the at least one of the fins.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Method, mobile device, and system for the message transmission of a vulnerable road user
    Patent number: 10665094
    Abstract: A method, a mobile device, and a system for message transmission of a vulnerable road user (VRU) are provided. The method is adapted to a first mobile device of a first VRU and includes the following steps. Whether there exists a target mobile device within a preset range of the first VRU is determined, where the target mobile device is a mobile device that has already broadcast a personal safety message (PSM). When the target mobile device exists within the preset range, whether to broadcast a first PSM is determined according to a relative distance between the target mobile device and an intersection as well as a relative distance between the target mobile device and the first mobile device. When the target mobile device doesn't exist within the preset range, the first PSM is broadcast.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 26, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Jing Lee, Po-Chun Kang, Tzu-Hsiang Su, Chia-Tai Tsai
  • Semiconductor Device Having Merged Epitaxial Features with Arc-Like Bottom Surface and Method of Making the Same
    Publication number: 20200161185
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature directly over the first fin, and a second lower semiconductor feature directly over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate. The semiconductor also further includes an upper semiconductor feature directly over and in physical contact with the first and second lower semiconductor features. The semiconductor device further includes a dielectric layer on sidewalls of the first and second lower semiconductor features.
    Type: Application
    Filed: January 27, 2020
    Publication date: May 21, 2020
    Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
  • METHOD OF FORMING SHAPED SOURCE/DRAIN EPITAXIAL LAYERS OF A SEMICONDUCTOR DEVICE
    Publication number: 20200135903
    Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Yi-Jing LEE, Ming-Hua YU
  • METHOD OF METAL GATE FORMATION AND STRUCTURES FORMED BY THE SAME
    Publication number: 20200135589
    Abstract: A method of forming a semiconductor structure includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; removing the barrier layer from the first trench to expose the dielectric layer; depositing a work function layer over the dielectric layer in the first trench; and depositing a conductive layer over the work function layer in the first trench.
    Type: Application
    Filed: April 1, 2019
    Publication date: April 30, 2020
    Inventors: YI-JING LEE, YA-YUN CHENG, HAU-YU LIN, I-SHENG CHEN, CHIA-MING HSU, CHIH-HSIN KO, CLEMENT HSINGJEN WANN
  • MANUFACTURING METHOD OF INTEGRATED CIRCUIT
    Publication number: 20200119006
    Abstract: A method for manufacturing an integrated circuit is provided. The method includes forming first and second semiconductor fins; forming first and second dielectric fin sidewall structures on opposite sidewalls of the first semiconductor fin, wherein the first dielectric fin sidewall structure is higher than the second dielectric fin sidewall structure, and the second dielectric fin sidewall structure is between the first and second semiconductor fins; recessing at least a portion of the first semiconductor fin between the first and second dielectric fin sidewall structures until a top of the recessed portion of the first semiconductor fin is lower than a top of the first dielectric fin sidewall structure; and forming a first epitaxy structure on the recessed portion of the first semiconductor fin.
    Type: Application
    Filed: December 13, 2019
    Publication date: April 16, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing LEE, Kun-Mu LI, Ming-Hua YU, Tsz-Mei KWOK
  • FIN FIELD-EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME
    Publication number: 20200119165
    Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
    Type: Application
    Filed: December 13, 2019
    Publication date: April 16, 2020
    Inventors: Yi-Jing Lee, Ming-Hua Yu
  • FinFET devices with unique shape and the fabrication thereof
    Patent number: 10622261
    Abstract: A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Integrated nanowire array devices for detecting and/or applying electrical signals to tissue
    Patent number: 10603493
    Abstract: An integrated nanowire device includes a first array of nanowires having a first set of characteristics and a second array of nanowires having a second set of characteristics. A processor is electrical communication with the first and second arrays of nanowires receives the first plurality of charges and generate a processor signal therefrom. The second array of nanowires may be configured to produce a stimulation current in response to the processor signal. The first or second array may be used to generate power for operation of the device, or the arrays may function as a stimulator, sensor combination to enable the device to self-regulate based on localized responses to stimulation. The device may be implanted for use as a neural stimulator.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 31, 2020
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Gabriel A. Silva, Massoud L. Khraiche, Gert Cauwenberghs, Yu-Hwa Lo, William R. Freeman, Sohmyung Ha, Yi Jing, E. J. Chichilnisky
  • Structure and Method for Semiconductor Device
    Publication number: 20200075597
    Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; two first fins in an N-type region of the semiconductor device; and two second fins in a P-type region of the semiconductor device. Each of the two first fins has a channel region and two source/drain (S/D) regions sandwiching the channel region. The semiconductor device further includes a gate stack engaging the channel regions of the two first fins; and four S/D features over the S/D regions of the two first fins. Each of the four S/D features includes a lower portion and an upper portion over the lower portion. Each of the lower portions of the four S/D features has a cross-sectional profile that is wider at its bottom than at its top. The upper portions of the four S/D features merge into two merged S/D features with one on each side of the gate stack.
    Type: Application
    Filed: October 31, 2019
    Publication date: March 5, 2020
    Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu
  • FinFET Semiconductor Device with Germanium Diffusion Over Silicon Fins
    Publication number: 20200035789
    Abstract: A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor material, replacing a first portion of at least one of the fins with a second semiconductor material, and distributing the second semiconductor material from the first portion to a second portion of the at least one of the fins.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Semiconductor device having merged epitaxial features with arc-like bottom surface and method of making the same
    Patent number: 10546784
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
  • SEMICONDUCTOR DEVICE AND METHOD
    Publication number: 20200020597
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Inventors: Yi-Jing Lee, Tsung-Hsi Yang, Ming-Hua Yu
  • Increasing Source/Drain Dopant Concentration to Reduced Resistance
    Publication number: 20200006532
    Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.
    Type: Application
    Filed: September 6, 2019
    Publication date: January 2, 2020
    Inventors: Yi-Jing Lee, Ming-Hua Yu