Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.

Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.

Abstract: An integrated circuit includes first and second semiconductor fins, first and second epitaxy structures, and first and second dielectric fin sidewall structures. The first and second epitaxy structures are respectively on the first and second semiconductor fins. The first epitaxy structure and the second epitaxy structure are merged together. The first and second dielectric fin sidewall structures are respectively on opposite first and second sidewalls of the first epitaxy structure. The first sidewall of the first epitaxy structure faces the second epitaxy structure. The first dielectric fin sidewall structure is shorter than the second dielectric fin sidewall structure.

Abstract: A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor material, replacing a first portion of at least one of the fins with a second semiconductor material, and distributing the second semiconductor material from the first portion to a second portion of the at least one of the fins.

Abstract: The disclosure provides a storage medium, an expansion base and an operation method thereof combined with a portable electronic device. The portable electronic device is pre-installed with an application program and includes a touch screen. The expansion base is paired with the portable electronic device and accommodates the portable electronic device. When the portable electronic device is accommodated inside the expansion base, a touch window on the surface of the expansion base exposes at least a portion of the touch screen, and the portable electronic device executes the application program to automatically adjust a size or a display position of a display image of the touch screen to correspond to the touch window.

Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.

Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, two fins over the substrate and protruding out of the isolation structure, and an epitaxial feature over the two fins. The epitaxial feature includes two lower portions and one upper portion. The two lower portions are over the two fins respectively. The upper portion is over the two lower portions and connects the two lower portions. The upper portion has a different dopant concentration than the two lower portions. A top surface of the upper portion is substantially flat.

Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Abstract: An intention inference system includes, a morphological analyzer to perform morphological analysis for a complex sentence with multiple intentions involved, a syntactic analyzer to perform syntactic analysis for the complex sentence morphologically analyzed by the morphological analyzer and to divide it into the first simple sentence and the second simple sentence, an intention inference unit to infer the first intention involved in the first simple sentence and the second intention involved in the second simple sentence, a feature extractor to extract as the first feature a morpheme showing execution order of operations involved in the first simple sentence and to extract as the second feature a morpheme showing execution order of operations involved in the second simple sentence, and an execution order inference unit to infer the execution order of the first operation corresponding to the first intention and the second operation corresponding to the second intention on the basis of the first feature and the

Abstract: The invention includes a glass plate, a bezel layer, a touch sensor layer and a signal wire layer. The bezel layer attached on a periphery of the glass plate defines a shaded area and a visible area. The touch sensor layer has sensing columns arranged in the visible area. Each of the sensing columns includes a common sensing electrode and a plurality of driving electrodes. The driving electrodes are divided into two electrode columns. Each driving electrode of the electrode columns is connected to a bridging point in one of two opposite side of the shaded area through a connecting wire. All the bridging points in a line are electrically connected by a bridging film connected to a part of the contacts of the connecting port through the signal wire layer. The common sensing electrodes are electrically connected to another part of the contacts through the signal wire layer.

Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.

Abstract: A method for determining the position of a mobile node applied to a roadside unit (RSU) is provided. The RSU and a plurality of mobile nodes form a communication network of a road. The method includes the steps of: obtaining, by, via at least one sensor, first road information, wherein the first road information provides absolute position distribution information associated with the mobile nodes; receiving, by a communication device, second road information from a first mobile node of the mobile nodes, wherein the second road information provides relative position distribution information associated with the first mobile node and second mobile nodes adjacent to the first mobile node; and determining, by a comparison device, the position of the first mobile node on the road according to the first road information and the second road information.

Abstract: A semiconductor device includes a transistor, an isolation structure, and a fin sidewall structure. The transistor includes a fin extending from a substrate and an epitaxy structure grown on the fin. The isolation structure is above the substrate. The fin sidewall structure is above the isolation structure and is on a sidewall of the epitaxy structure. A method for manufacturing the semiconductor device is also disclosed.

Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.

Abstract: A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.

Abstract: A direct emitting LED illumination module for eliminating chromatic dispersion improves a vehicular LED lamp to comply with related regulations. The LED illumination module includes a LED light source and a plano-convex lens. The LED light source is located at the focus of the plano-convex lens. The LED light source emits light to the plane of the plano-convex lens, and the light exits from the convex surface of the plano-convex lens. The plano-convex lens focuses the light to form a desirable light pattern. Besides, the plane of the plano-convex lens has a microstructure thereon to suppress the angular correlated color temperature deviation of the light pattern and eliminate chromatic dispersion.

Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.