Patents by Inventor Yi Lin

Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250048530
    Abstract: Disclosed is an electronic assembly that includes a heat sink with a groove that is cut on a surface of the heat sink. A thermal interface material is disposed between the heat sink and an electronic device. A compressible filler disposed in the groove surrounds and confines the thermal interface material.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 6, 2025
    Inventors: Yi-Kuan LIAO, Kuan-Lin PENG
  • Publication number: 20250048763
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
  • Publication number: 20250045736
    Abstract: Certain aspects of the present disclosure provide techniques for securely accessing a wallet on a blockchain. An example method generally includes receiving a request to access a wallet on a blockchain. The request generally includes an authorization code associated with the wallet and user credentials associated with an owner of the wallet. A first portion of a private key is decrypted based on the authorization code and a salt associated with the user credentials, and a second portion of the private key is decrypted based on credentials associated with an application through which the wallet is accessed. Access to the wallet is granted based on the decrypted first portion and the decrypted second portion of the private key.
    Type: Application
    Filed: August 1, 2024
    Publication date: February 6, 2025
    Inventors: Ming Chang DONG, Huaiting HUANG, Ming Chang SHIH, Zhiyu ZHANG, Chi Huang FAN, Jordan FORSSMAN, Jayaprakash PAKALAPATI, Ka Wai TSUI, Gagneet Singh MAC, Yi-An LIN, Li TAO, Chiang HAN-ZHEN, Tzuyu HSU, Liu Chien WEI, Debra PENG, Nikhil KUMAR, Kok Peng LIM, Andrew ZIMMER, Justin BELL, Yingying ZHENG
  • Publication number: 20250046655
    Abstract: A method includes finding a first plurality of through-silicon vias from a first layout of a wafer, and finding a second plurality of through-silicon vias from the first plurality of through-silicon vias. The second plurality of through-silicon vias are connected in parallel. The second plurality of through-silicon vias are merged into a large through-silicon via to generate a second layout of the wafer.
    Type: Application
    Filed: November 30, 2023
    Publication date: February 6, 2025
    Inventors: Chao Yi Lin, Kuo-Yen Liu, Chih-Hsiang Yao
  • Publication number: 20250043136
    Abstract: A novel rheology modifier which comprises a quaternary ammonium containing polyamide for use in aqueous paint, and that can provide excellent pigment suspension and rheological properties to the aqueous based coating without being affected by pH fluctuation.
    Type: Application
    Filed: July 24, 2023
    Publication date: February 6, 2025
    Applicant: ELEMENTIS SPECIALTIES, INC.
    Inventors: Chun-Hung Yen, Wei-Jen Huang, Ming-Jhe Li, Yu-Lun Hung, Hou-Jen Yen, Yu-Yen Lu, Yu-Zhe Su, Hung-Yi Lin
  • Publication number: 20250046961
    Abstract: A lithium battery cell includes an upper cover module, a first battery electrode group, a second battery electrode group, and a plurality of first electrode connection straps. The first electrode connection straps are stacked together. A first end of the first electrode connection straps is welded to a first tab, a second end of the first electrode connection straps is welded to a second tab, and a middle part of the first electrode connection straps is welded to a first electrode terminal. An even number of first bending parts are formed between the middle part and the first end, and an even number of second bending parts are formed between the middle part and the second end, and the first bending parts and the second bending parts are symmetrical to each other. A lithium battery cell manufacturing method is also disclosed therein.
    Type: Application
    Filed: October 25, 2024
    Publication date: February 6, 2025
    Inventors: Cheng-Huang CHEN, Yi-Hsiang CHAN, Shu-Lin CHEN, Wei-En HSU
  • Publication number: 20250045743
    Abstract: Certain aspects of the present disclosure provide techniques for securely accessing a wallet maintained by a centralized platform on a blockchain. An example method generally includes receiving a request to access one or more wallets on a blockchain. Generally, the request includes an authorization code associated with a controlling party associated with the one or more wallets and user credentials associated with the controlling party. A first portion of a private key is decrypted based on the authorization code and a salt associated with the user credentials associated with the controlling party, and a second portion of the private key is decrypted based on credentials associated with an application through which the wallet is accessed. Access to the one or more wallets is granted based on the decrypted first portion and the decrypted second portion of the private key.
    Type: Application
    Filed: August 1, 2024
    Publication date: February 6, 2025
    Inventors: Huaiting HUANG, Ming Chang SHIH, Zhiyu ZHANG, Chi Huang FAN, Jordan FORSSMAN, Jayaprakash PAKALAPATI, Ka Wai TSUI, Gagneet Singh MAC, Yi-An LIN, Li TAO, Nikhil KUMAR, Kok Peng LIM, Hsuan Ming LI, Andrew ZIMMER, Justin BELL, Yingying ZHENG
  • Publication number: 20250044710
    Abstract: A method of image template matching for multiple process layers of, for example, semiconductor substrate with an adaptive weight map is described. An image template is provided with a weight map, which is adaptively updated based during template matching based on the position of the image template on the image. A method of template matching a grouped pattern or artifacts in a composed template is described, wherein the pattern comprises deemphasized areas weighted less than the image templates. A method of generating an image template based on a synthetic image is described. The synthetic image can be generated based on process and image modeling. A method of selecting a grouped pattern or artifacts and generating a composed template is described. A method of per layer image template matching is described.
    Type: Application
    Filed: December 13, 2022
    Publication date: February 6, 2025
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Jiyou FU, Jing SU, Chenxi LIN, Jiao LIANG, Guangqing CHEN, Yi ZOU
  • Patent number: 12215414
    Abstract: Some implementations described herein provide a shutter disc for use during a conditioning process within a processing chamber of a deposition tool. The shutter disc described herein includes a material having a wave-shaped section to reduce heat transfer to the shutter disc and to provide relief from thermal stresses. Furthermore, the shutter disc includes a deposition of a thin-film material on a backside of the shutter disc, where a diameter of the shutter disc causes a spacing between an inner edge of the thin-film material and an outer edge of a substrate support component. The spacing prevents an accumulation of material between the thin film material and the substrate support component, reduces tilting of the shutter disc due to a placement error, and reduces heat transfer to the shutter disc.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lin Wang, Chin-Szu Lee, Hua-Sheng Chiu, Yi-Chao Chang, Zih-Shou Mue
  • Patent number: 12215934
    Abstract: A thermal module structure includes an aluminum base having an upper and a lower surface, at least one L-shaped copper heat pipe, a first aluminum fin assembly, a second aluminum fin assembly, and at least one copper embedding layer. The copper heat pipe includes a heat absorption section fitted on the aluminum base, and a heat dissipation section connected to the second aluminum fin assembly. The copper embedding layers are provided on the aluminum base at areas corresponding to the first aluminum fin assembly and the heat absorption section of the copper heat pipe, and on a bottom surface of the first aluminum fin assembly that is to be connected to the aluminum base. Thus, the first aluminum fin assembly and the copper heat pipe can be directly welded to the aluminum base via the copper embedding layers without the need of electroless nickel plating.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: February 4, 2025
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventors: Sheng-Huang Lin, Yuan-Yi Lin
  • Patent number: 12216485
    Abstract: An output circuit includes an output driver, a voltage regulator, a control circuit and a charge pump circuit. The output driver includes a signal input terminal, a signal output terminal and a first power receiving terminal. The voltage regulator is coupled to the first power receiving terminal of the output driver. The control circuit is coupled to the signal input terminal of the output driver. The charge pump circuit is coupled to the control circuit and the first power receiving terminal of the output driver.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 4, 2025
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Jen-Yi Lin
  • Patent number: 12216980
    Abstract: A method includes the following operations: identifying a layer of a first layout based on a first violation generated on the layer; generating a metal density value associated with the layer; when the metal density value is larger than or equal to a preset value, classifying the first violation into a first class corresponding to routing congestions of the first layout; when the first violation is classified into the first class, assigning, to the first violation, a first operation of a plurality of first pre-stored operations corresponding to the first class; and performing the first operation to the first layout to generate a second layout.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 4, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Yi-Lin Chuang, Song Liu, Pei-Pei Chen, Heng-Yi Lin, Shih-Yao Lin, Chin-Hsien Wang
  • Patent number: 12218199
    Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Jia-Ming Lin, Chi On Chui
  • Patent number: 12217999
    Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Lei Chen, Cheng-Hsin Chen, Chung Chieh Ting, Che-Yi Lin, Clark Lee
  • Patent number: 12216218
    Abstract: Embodiments of this application provide a positioning method and apparatus. The method may include setting an ambiguity adjustment parameter for a mobile device, where the ambiguity adjustment parameter is used to record an ambiguity change status used to determine a virtual station observation value for the mobile device. The method may also include adjusting an observation value of a first primary datum station based on a first ambiguity adjustment parameter of the mobile device in a first serving cell to generate a first virtual station observation value, where the first primary datum station is a primary datum station of the first serving cell, and the first virtual station observation value is used to position the mobile device in the first serving cell; and sending the first virtual station observation value to the mobile device.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: February 4, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jingsong Huang, Rui Yuan, Yangbo Lin, Yi Zhang
  • Patent number: 12217232
    Abstract: The present disclosure concerns methods and systems for increasing anonymity and traceability of a digital property management system that manages digital property transactions on a distributed transaction consensus network. The digital property management system comprises a sender's digital property manager and a recipient's digital property manager. The sender's digital property manager further comprises a sender's module and a sender's transaction node and the recipient's digital property manager further comprises a recipient' module and a recipient's transaction node. To increase anonymity of a remittance transaction between, sender's module is not allowed to access a recipient's virtual identification. Thus, recipient's module generates a token to temporarily replace a recipient's virtual identification. To increase anonymity, an encrypted label is generated for each sub-transaction to identify sub-transactions and their sequence in the same remittance set.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: February 4, 2025
    Inventors: William Wu, Brian Chan, Chiahsin Li, See Neng Foo, Ling Wu, Huan-Yi Lin
  • Patent number: 12218075
    Abstract: A package structure includes an encapsulant, a patterned circuit structure, at least one electronic component and a shrinkage modifier. The patterned circuit structure is disposed on the encapsulant and includes a pad. The electronic component is disposed on the patterned circuit structure, and includes a bump electrically connected to the pad. The shrinkage modifier is encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: February 4, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hsu-Chiang Shih, Hung-Yi Lin, Chien-Mei Huang
  • Patent number: 12217989
    Abstract: A semiconductor apparatus and a method for collecting residues of curable material are provided. The semiconductor apparatus includes a chamber containing a wafer cassette, and a collecting module disposed in the chamber for collecting residues of curable material in the chamber. The collecting module includes a flow-directing structure disposed below a ceiling of the chamber, a baffle structure disposed below the flow-directing structure, and a tray disposed on the wafer cassette. The flow-directing structure includes a first hollow region, the baffle structure includes a second hollow region, and the tray is moved together with the wafer cassette to pass through the second hollow region of the baffle structure and is positioned to cover the first hollow region of the flow-directing structure.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Cheng Lin, Pin-Yi Hsin, Ching Shun Lee, Bo-Han Huang, Cheng-tsung Tu
  • Patent number: 12219879
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: D1060221
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: February 4, 2025
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yau-Tzung Van, Li-Cheng Chiang, Jung-Yi Huang, Hung-Chang Lin