Patents by Inventor Yi Pei

Yi Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12278293
    Abstract: The present disclosure discloses a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a doped epitaxial layer located on one side of the substrate, a channel layer located on one side of the doped epitaxial layer away from the substrate, a potential barrier layer located on one side of the channel layer away from the doped epitaxial layer, and a first electrode and a second electrode located on one side of the potential barrier layer away from the channel layer, wherein the first electrode penetrates the potential barrier layer, the channel layer and part of the doped epitaxial layer, the first electrode forms a Schottky contact with the channel layer, and a resistance of the part of the doped epitaxial layer in contact with the first electrode is greater than a resistance of the channel layer.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: April 15, 2025
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Guangmin Deng, Yi Pei
  • Patent number: 12272743
    Abstract: The present disclosure discloses a semiconductor device, a method of manufacturing the same, and a semiconductor package structure. The semiconductor device including a substrate, a multilayer semiconductor layer located on one side of the substrate, in which a Two-Dimensional Electron Gas is formed, a first source, a first gate and a first drain located on one side of the multilayer semiconductor layer and located within an active region of the multilayer semiconductor layer, the first gate being located between the first source and the first drain, and a back surface gate contact electrode located on one side of the substrate away from the multilayer semiconductor layer, wherein the first gate is electrically connected to the back surface gate contact electrode. A signal is provided from the back surface of the semiconductor device to the first gate, to reduce the parasitic inductance and parasitic resistance caused by the device during the packaging process.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: April 8, 2025
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Junfeng Wu, Xingxing Wu, Yi Pei
  • Publication number: 20250113579
    Abstract: Embodiments of the present disclosure disclose a semiconductor device including a plurality of sources, a plurality of gates, and a plurality of drains located in an active area. In the active area, the sources, the gates, and the drains are alternately arranged along a first direction, and along the first direction, the sources include two sources respectively closest to ends of the arrangement, and any one of the gates is located between one of the sources and one of the drains, a length of at least a source located at the center along the first direction is greater than lengths of sources located at both ends along the first direction. The semiconductor device further includes a plurality of rows of through holes extending through a substrate and a multilayer semiconductor layer, a plurality of rows of the through holes are arranged along the first direction, and an orthographic projection.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 3, 2025
    Inventors: Naiqian ZHANG, Yi PEI, Linlin SUN, Xinchuan ZHANG
  • Publication number: 20250002599
    Abstract: The disclosure provides binding proteins that bind PD-L1 and CD137 (PD-L1/CD137 bispecific), binding proteins that bind PD-L1 and TGF? (PD-L1/TGF? bispecific), binding proteins that bind PD-L1, TGF?, and CD137 (PD-L1/TGF?/CD137 trispecific), and binding proteins that bind CD137, TGF?, and PD-L1 (CD137/TGF?/PD-L1 trispecific). The disclosure also provides pharmaceutical compositions comprising these binding proteins, and methods of their use to treat and/or prevent cancer.
    Type: Application
    Filed: September 1, 2022
    Publication date: January 2, 2025
    Inventors: Yi Pei, Haichun Huang, Yick Loi, Chang Hung Chen, Han Li, Di SHEN, Ming LEI
  • Patent number: 12152150
    Abstract: The disclosure discloses a high-viscosity, high-elasticity, and anti-aging composite modified asphalt and a preparation method thereof, belongs to the technical field of road engineering materials, and solves the technical problem that the comprehensive performance of an existing asphalt ultrathin wearing layer needs to be further improved so as to prolong the service life of a pavement surface layer and reduce the pavement maintenance costs. The composite modified asphalt is prepared from the following components in parts by mass: 100 parts of a matrix asphalt, 10 to 15 parts of a thermoplastic styrene-butadiene rubber, 5 to 8 parts of a tackifier, 0.5 to 1.5 parts of a plasticizer, 2 to 5 parts of a compatibilizer, 0.1 to 0.4 parts of a stabilizer, and 0.01 to 0.05 parts of an anti-aging agent. The composite modified asphalt prepared by the disclosure has the advantages of high elasticity, high viscosity, excellent aging resistance, etc.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: November 26, 2024
    Assignee: Sichuan Road and Bridge Construction Group Co., Ltd.
    Inventors: Shuangquan Jiang, Jian Yang, Peilong Li, Wei Lu, Liuda Cheng, Yi Pei, Zhan Ding, Jianglin Du, Haiqing Li, Jixiang Pu, Qingyun Li, Maoqin Niu, Jianming Zhang, Wanchun Liu
  • Publication number: 20240383978
    Abstract: The present disclosure provides bispecific binding proteins and fragments thereof which bind to human CD137 and a tumor associated antigen (e.g., Claudin-6, Claudin 18.2, or Nectin-4), to polynucleotide sequences encoding these antibodies and to cells producing them. The disclosure further relates to therapeutic compositions comprising these antibodies, and to methods of their use for cancer detection, prognosis and antibody-based immunotherapy.
    Type: Application
    Filed: September 1, 2022
    Publication date: November 21, 2024
    Inventors: Yi Pei, Ming Lei, Haichun Huang, Yick Loi, Chang Hung Chen, Han LI
  • Publication number: 20240379579
    Abstract: Embodiments of the present disclosure disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes an active region and a passive region surrounding the active region. The semiconductor device further includes a substrate, a multi-layer semiconductor layer located on one side of the substrate, and at least one shielding structure located on one side of the substrate, the shielding structure being electrically connected to a preset potential, for forming an electric field or a zero electric field of the active region pointing toward the passive region.
    Type: Application
    Filed: December 29, 2021
    Publication date: November 14, 2024
    Inventors: Yi PEI, Xiao HAN, Yuan LI, Guangze XU
  • Patent number: 12142537
    Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an energy sensing film. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The energy sensing film is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the energy sensing film is contacted with an external energy source, and the induced charge is stored in the floating gate.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: November 12, 2024
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Burn-Jeng Lin, Chrong-Jung Lin, Ya-Chin King, Yi-Pei Tsai
  • Publication number: 20240270968
    Abstract: The disclosure discloses a high-viscosity, high-elasticity, and anti-aging composite modified asphalt and a preparation method thereof, solves the technical problem that the comprehensive performance of an existing asphalt ultrathin wearing layer needs to be further improved so as to prolong the service life of a pavement surface layer and reduce the pavement maintenance costs. The composite modified asphalt is prepared from the following components in parts by mass: 100 parts of a matrix asphalt, 10 to 15 parts of a thermoplastic styrene-butadiene rubber, 5 to 8 parts of a tackifier, 0.5 to 1.5 parts of a plasticizer, 2 to 5 parts of a compatilizer, 0.1 to 0.4 parts of a stabilizer, and 0.01 to 0.05 parts of an anti-aging agent. The composite modified asphalt prepared by the disclosure has the advantages of high elasticity, high viscosity, excellent aging resistance, etc.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 15, 2024
    Inventors: Shuangquan JIANG, Jian YANG, Peilong LI, Wei LU, Liuda CHENG, Yi PEI, Zhan DING, Jianglin DU, Haiqing LI, Jixiang PU, Qingyun LI, Maoqin Niu
  • Publication number: 20240067740
    Abstract: The present disclosure provides antibodies and antibody fragments thereof that bind to human TNFR2. The disclosed antibodies, inhibit the TNF-TNFR2 signaling axis and enhance cytokine secretion in T effector cells and are therefore useful for the treatment of cancer, either alone or in combination with other agents.
    Type: Application
    Filed: December 30, 2021
    Publication date: February 29, 2024
    Inventors: Yi PEI, Haichun HUANG, Ming LEI, Han LI, Chi Shing SUM, Alla PRITSKER, Bor-Ruei LIN, Fangqiang TANG
  • Publication number: 20230396185
    Abstract: The present disclosure discloses a dual output energy conversion device, modulation method, and power supply device which can enhance the bus voltage boosting capability of the conversion device by using a first electric energy storage module, so that it can be used in a wider input voltage range. A first conversion output circuit and a second conversion output circuit are set, and voltage stress of all switching tubes is reduced to half of the direct current bus voltage, which can greatly reduce the system EMI of the conversion device in high-frequency applications, and improve the power conversion efficiency of the device. The dual output energy conversion device only needs to realize the control of one-stage power conversion, and has a simple control structure.
    Type: Application
    Filed: October 28, 2021
    Publication date: December 7, 2023
    Inventors: Mao HU, Yi PEI
  • Publication number: 20230331867
    Abstract: The present disclosure provides antibodies and antibody fragments thereof that bind to Nectin-4. Such antibodies and antibody fragments are useful for the treatment of cancer, either alone or in combination with other agents.
    Type: Application
    Filed: September 3, 2021
    Publication date: October 19, 2023
    Inventors: Yi PEI, Haichun HUANG, Ming LEI, Han LI
  • Publication number: 20230272063
    Abstract: Antibodies that specifically bind to the human tight junction molecule CLDN18.2 and have functional properties that make them suitable for use in antibody-based immunotherapies of a disease associated with aberrant expression of CLDN18.2 are disclosed.
    Type: Application
    Filed: July 13, 2022
    Publication date: August 31, 2023
    Inventors: Han Li, Ming Lei, Yi Pei, Haichun Huang
  • Publication number: 20230178616
    Abstract: Embodiments of the present disclosure disclose a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and a passive region, the semiconductor device further includes a substrate, a multilayer semiconductor layer, and a source, a gate and a drain, the gate being located between the source and the drain, wherein, in a first direction, the gate includes, in turn, a first end portion, an intermediate portion and a second end portion, the intermediate portion, the source and the drain all being located in the active region, and the first end portion and/or the second end portion extending into the passive region, and in a second direction, an extension width of a portion at least located in the passive region of the first end portion and/or the second end portion is greater than an extension width of the intermediate portion.
    Type: Application
    Filed: March 24, 2021
    Publication date: June 8, 2023
    Inventors: Naiqian ZHANG, Yi PEI
  • Publication number: 20230170214
    Abstract: Embodiments of the present disclosure provide an epitaxial structure of a semiconductor device and a method of manufacturing the same. The epitaxial structure includes a substrate, and an epitaxial layer located on a side of the substrate, the epitaxial layer including a nucleation layer located on a side of the substrate and a buffer layer located on a side of the nucleation layer away from the substrate, wherein a thickness of the buffer layer is inversely proportional to a thickness of the nucleation layer.
    Type: Application
    Filed: June 9, 2021
    Publication date: June 1, 2023
    Inventors: Hui ZHANG, Shiqiang LI, Naiqian ZHANG, Yi PEI
  • Publication number: 20230081211
    Abstract: Disclosed are a semiconductor device and a preparation method thereof. The semiconductor device includes a substrate; a multilayer semiconductor layer located on a side of the substrate; and a source, a gate, a drain and a field plate structure located on a side, away from the substrate, of the multilayer semiconductor layer. The field plate structure includes a main body portion and a first extension portion; the main body portion is located between the gate and the drain; the first extension portion is connected to the main body portion and is located on a side, away from the multilayer semiconductor layer, of the gate; and the first extension portion at least partially overlaps the gate. By adopting the above technical solution, the probability of the breakdown, which occurs at the side of the gate near the drain, may be reduced, thereby increasing the reliability of semiconductor devices.
    Type: Application
    Filed: November 18, 2022
    Publication date: March 16, 2023
    Applicant: Dynax Semiconductor, Inc.
    Inventors: Yi PEI, Jian LIU, Xingxing WU
  • Publication number: 20230080399
    Abstract: An electrical connection base providing support for heavy expansion cards includes a pedestal and a supporting element. A socket is defined on the pedestal. The supporting element includes installation and support portion. A through hole is defined on the installation portion, which is portion set outside the pedestal, the pedestal entering the through hole. The support portion has a first slot, and the first slot runs through the end of the support portion away from the installation portion. The portion of the expansion card or other element plugged into the socket and outside the pedestal is inserted into the first slot. The groove wall of the first slot is in contact with the element, the support portion thereby supports the card or element and prevents strain and deformation.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 16, 2023
    Inventors: YI-PEI HSIAO, HSIANG-YU LIEN, TUNG-HO SHIH
  • Publication number: 20230067757
    Abstract: Antibodies that specifically bind to the human tight junction molecule CLDN18.2 and have functional properties that make them suitable for use in antibody-based immunotherapies of a disease associated with aberrant expression of CLDN18.2 are disclosed.
    Type: Application
    Filed: June 22, 2022
    Publication date: March 2, 2023
    Inventors: Han Li, Ming Lei, Yi Pei, Haichun Huang
  • Publication number: 20230019524
    Abstract: Disclosed are an epitaxial structure of a semiconductor device, a manufacturing method, and a semiconductor device. The epitaxial structure includes a substrate and a semiconductor layer; the semiconductor layer includes a buffer layer; the buffer layer includes a first buffer subsection and a second buffer subsection which are connected to each other and arranged along a direction from a source preset region to a drain preset region, and a vertical projection on the substrate of the first buffer subsection overlaps with a vertical projection on the substrate of the source preset region, and a vertical projection on the substrate of the second buffer subsection overlaps with a vertical projection on the substrate of each of the gate preset region and the drain preset region; an ion implant concentration in the second buffer subsection is greater than or equal to an ion implant concentration in the first buffer subsection.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 19, 2023
    Applicant: Dynax Semiconductor Inc.
    Inventors: Hongtu QIAN, Yi PEI, Hui ZHANG
  • Patent number: 11538729
    Abstract: Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: December 27, 2022
    Assignee: DYNAX SEMICONDUCTOR, INC.
    Inventors: Yi Pei, Guochun Kang, Linlin Sun