Patents by Inventor Yi Pei

Yi Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12278293
    Abstract: The present disclosure discloses a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a doped epitaxial layer located on one side of the substrate, a channel layer located on one side of the doped epitaxial layer away from the substrate, a potential barrier layer located on one side of the channel layer away from the doped epitaxial layer, and a first electrode and a second electrode located on one side of the potential barrier layer away from the channel layer, wherein the first electrode penetrates the potential barrier layer, the channel layer and part of the doped epitaxial layer, the first electrode forms a Schottky contact with the channel layer, and a resistance of the part of the doped epitaxial layer in contact with the first electrode is greater than a resistance of the channel layer.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: April 15, 2025
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Guangmin Deng, Yi Pei
  • Publication number: 20250118643
    Abstract: A semiconductor device has a first substrate with a surface. A thickness of the first substrate is less than 120 micrometers. The surface undergoes a grinding operation. The surface of the first substrate is then polished to produce a polished surface. The first substrate is singulated into a plurality of semiconductor die. The semiconductor die is over an interposer. The interposer has a second substrate and a conductive via formed through the second substrate. The interposer further has a first insulating layer formed over a first surface of the second substrate, first conductive layer formed over the first surface, second insulating layer formed over a second surface of the second substrate, second conductive layer formed over the second surface, and bump formed over the second conductive layer. An underfill material is deposited around the semiconductor die. The polished surface inhibits progression of the underfill material onto the polished surface.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 10, 2025
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yi Jing Eric Chong, Marites Roque, Rowena Zarate, Linda Pei Ee Chua, Kai Chong Chan
  • Patent number: 12272743
    Abstract: The present disclosure discloses a semiconductor device, a method of manufacturing the same, and a semiconductor package structure. The semiconductor device including a substrate, a multilayer semiconductor layer located on one side of the substrate, in which a Two-Dimensional Electron Gas is formed, a first source, a first gate and a first drain located on one side of the multilayer semiconductor layer and located within an active region of the multilayer semiconductor layer, the first gate being located between the first source and the first drain, and a back surface gate contact electrode located on one side of the substrate away from the multilayer semiconductor layer, wherein the first gate is electrically connected to the back surface gate contact electrode. A signal is provided from the back surface of the semiconductor device to the first gate, to reduce the parasitic inductance and parasitic resistance caused by the device during the packaging process.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: April 8, 2025
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Junfeng Wu, Xingxing Wu, Yi Pei
  • Publication number: 20250113579
    Abstract: Embodiments of the present disclosure disclose a semiconductor device including a plurality of sources, a plurality of gates, and a plurality of drains located in an active area. In the active area, the sources, the gates, and the drains are alternately arranged along a first direction, and along the first direction, the sources include two sources respectively closest to ends of the arrangement, and any one of the gates is located between one of the sources and one of the drains, a length of at least a source located at the center along the first direction is greater than lengths of sources located at both ends along the first direction. The semiconductor device further includes a plurality of rows of through holes extending through a substrate and a multilayer semiconductor layer, a plurality of rows of the through holes are arranged along the first direction, and an orthographic projection.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 3, 2025
    Inventors: Naiqian ZHANG, Yi PEI, Linlin SUN, Xinchuan ZHANG
  • Publication number: 20250112078
    Abstract: A semiconductor manufacturing equipment has a wafer tape including a plurality of alignment holes formed through the wafer tape. A semiconductor wafer is disposed over the wafer tape. The semiconductor wafer includes a circular or rectangular form-factor. A light source is disposed under the wafer tape. The semiconductor wafer is misaligned on the wafer tape with light passing through one or more alignment holes. The semiconductor wafer is centered on the wafer tape with no light passing through one or more alignment holes. The wafer tape has a plurality of wafer alignment markings for different size semiconductor wafers. A light detector is disposed over the semiconductor wafer to detect light passing through the wafer tape. A control arm can be attached to the semiconductor wafer to provide the ability to move the semiconductor wafer in response to a control signal from the light detector.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 3, 2025
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Tack Chee Yong, Yi Jing Eric Chong, Kok Lim Jason Ng, Linda Pei Ee Chua
  • Patent number: 12235197
    Abstract: An automatic processing device for liquid samples includes a sample region, a control module, an image identification device and a centrifuge. The sample region is configured to accommodate a plurality of centrifuge tubes. The control module includes a mechanical module. The mechanical module is configured to unscrew or tighten upper caps of the centrifuge tubes, and is configured to draw liquid from the centrifuge tubes or discharge liquid to the centrifuge tubes. The image identification device is coupled to the control module. The centrifuge is coupled to the control module. The centrifuge is configured to accommodate the centrifuge tubes and perform centrifugal treatment.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: February 25, 2025
    Assignees: CANCER FREE BIOTECH LTD., SONGYI SYSTEM CO., LTD.
    Inventors: Po-Han Chen, Shih-Pei Wu, Yi-Hsuan Chen, Chung-I Chen, Chun-Chieh Chiang, Chi-Ming Lee
  • Publication number: 20250042987
    Abstract: Provided are an anti-TSLP monoclonal antibody, an antigen-binding fragment thereof and a use thereof. The antibody has relatively high affinity with a TSLP antigen, may effectively inhibit the binding of the TSLP antigen to a receptor complex thereof, and then prevents a TSLP-targeted immune cell from releasing a pro-inflammatory cytokine, thereby asthma attack is prevented and asthma control is improved. The monoclonal antibody molecule obtained by screening in the present application also has relatively high thermal stability and relatively good safety. The present application may be used for treating asthma, chronic obstructive pulmonary disease, chronic eosinophilic pneumonia, idiopathic pulmonary fibrosis and allergic dermatitis; and the asthma includes severe asthma, eosinophilic or non-eosinophilic asthma, and low eosinophilic asthma.
    Type: Application
    Filed: November 18, 2022
    Publication date: February 6, 2025
    Inventors: Yi BAI, Shuang PEI, Si LIU
  • Patent number: 12216980
    Abstract: A method includes the following operations: identifying a layer of a first layout based on a first violation generated on the layer; generating a metal density value associated with the layer; when the metal density value is larger than or equal to a preset value, classifying the first violation into a first class corresponding to routing congestions of the first layout; when the first violation is classified into the first class, assigning, to the first violation, a first operation of a plurality of first pre-stored operations corresponding to the first class; and performing the first operation to the first layout to generate a second layout.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 4, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Yi-Lin Chuang, Song Liu, Pei-Pei Chen, Heng-Yi Lin, Shih-Yao Lin, Chin-Hsien Wang
  • Publication number: 20250035947
    Abstract: A zoom optical system includes a first lens, a transreflective coating layer, a liquid crystal layer, a substrate, a polarizing reflector film layer and a second lens. The first lens has a first surface and an opposite second surface. The transreflective coating layer adheres to the first surface of the first lens. The liquid crystal layer adheres to the second surface of the first lens. The substrate adheres to a surface facing away the first lens of the liquid crystal layer. The polarizing reflector film layer is located at a side of the substrate facing away the liquid crystal layer. The second lens adheres to the polarizing reflector film layer by an optical adhesive layer.
    Type: Application
    Filed: September 13, 2023
    Publication date: January 30, 2025
    Inventors: Yi Chen YANG, Ting Hui CHEN, Po Lun CHEN, Yun Pei CHEN
  • Publication number: 20250002599
    Abstract: The disclosure provides binding proteins that bind PD-L1 and CD137 (PD-L1/CD137 bispecific), binding proteins that bind PD-L1 and TGF? (PD-L1/TGF? bispecific), binding proteins that bind PD-L1, TGF?, and CD137 (PD-L1/TGF?/CD137 trispecific), and binding proteins that bind CD137, TGF?, and PD-L1 (CD137/TGF?/PD-L1 trispecific). The disclosure also provides pharmaceutical compositions comprising these binding proteins, and methods of their use to treat and/or prevent cancer.
    Type: Application
    Filed: September 1, 2022
    Publication date: January 2, 2025
    Inventors: Yi Pei, Haichun Huang, Yick Loi, Chang Hung Chen, Han Li, Di SHEN, Ming LEI
  • Patent number: 12152150
    Abstract: The disclosure discloses a high-viscosity, high-elasticity, and anti-aging composite modified asphalt and a preparation method thereof, belongs to the technical field of road engineering materials, and solves the technical problem that the comprehensive performance of an existing asphalt ultrathin wearing layer needs to be further improved so as to prolong the service life of a pavement surface layer and reduce the pavement maintenance costs. The composite modified asphalt is prepared from the following components in parts by mass: 100 parts of a matrix asphalt, 10 to 15 parts of a thermoplastic styrene-butadiene rubber, 5 to 8 parts of a tackifier, 0.5 to 1.5 parts of a plasticizer, 2 to 5 parts of a compatibilizer, 0.1 to 0.4 parts of a stabilizer, and 0.01 to 0.05 parts of an anti-aging agent. The composite modified asphalt prepared by the disclosure has the advantages of high elasticity, high viscosity, excellent aging resistance, etc.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: November 26, 2024
    Assignee: Sichuan Road and Bridge Construction Group Co., Ltd.
    Inventors: Shuangquan Jiang, Jian Yang, Peilong Li, Wei Lu, Liuda Cheng, Yi Pei, Zhan Ding, Jianglin Du, Haiqing Li, Jixiang Pu, Qingyun Li, Maoqin Niu, Jianming Zhang, Wanchun Liu
  • Publication number: 20240383978
    Abstract: The present disclosure provides bispecific binding proteins and fragments thereof which bind to human CD137 and a tumor associated antigen (e.g., Claudin-6, Claudin 18.2, or Nectin-4), to polynucleotide sequences encoding these antibodies and to cells producing them. The disclosure further relates to therapeutic compositions comprising these antibodies, and to methods of their use for cancer detection, prognosis and antibody-based immunotherapy.
    Type: Application
    Filed: September 1, 2022
    Publication date: November 21, 2024
    Inventors: Yi Pei, Ming Lei, Haichun Huang, Yick Loi, Chang Hung Chen, Han LI
  • Publication number: 20240379579
    Abstract: Embodiments of the present disclosure disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes an active region and a passive region surrounding the active region. The semiconductor device further includes a substrate, a multi-layer semiconductor layer located on one side of the substrate, and at least one shielding structure located on one side of the substrate, the shielding structure being electrically connected to a preset potential, for forming an electric field or a zero electric field of the active region pointing toward the passive region.
    Type: Application
    Filed: December 29, 2021
    Publication date: November 14, 2024
    Inventors: Yi PEI, Xiao HAN, Yuan LI, Guangze XU
  • Patent number: 12142537
    Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an energy sensing film. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The energy sensing film is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the energy sensing film is contacted with an external energy source, and the induced charge is stored in the floating gate.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: November 12, 2024
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Burn-Jeng Lin, Chrong-Jung Lin, Ya-Chin King, Yi-Pei Tsai
  • Publication number: 20240270968
    Abstract: The disclosure discloses a high-viscosity, high-elasticity, and anti-aging composite modified asphalt and a preparation method thereof, solves the technical problem that the comprehensive performance of an existing asphalt ultrathin wearing layer needs to be further improved so as to prolong the service life of a pavement surface layer and reduce the pavement maintenance costs. The composite modified asphalt is prepared from the following components in parts by mass: 100 parts of a matrix asphalt, 10 to 15 parts of a thermoplastic styrene-butadiene rubber, 5 to 8 parts of a tackifier, 0.5 to 1.5 parts of a plasticizer, 2 to 5 parts of a compatilizer, 0.1 to 0.4 parts of a stabilizer, and 0.01 to 0.05 parts of an anti-aging agent. The composite modified asphalt prepared by the disclosure has the advantages of high elasticity, high viscosity, excellent aging resistance, etc.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 15, 2024
    Inventors: Shuangquan JIANG, Jian YANG, Peilong LI, Wei LU, Liuda CHENG, Yi PEI, Zhan DING, Jianglin DU, Haiqing LI, Jixiang PU, Qingyun LI, Maoqin Niu
  • Publication number: 20240067740
    Abstract: The present disclosure provides antibodies and antibody fragments thereof that bind to human TNFR2. The disclosed antibodies, inhibit the TNF-TNFR2 signaling axis and enhance cytokine secretion in T effector cells and are therefore useful for the treatment of cancer, either alone or in combination with other agents.
    Type: Application
    Filed: December 30, 2021
    Publication date: February 29, 2024
    Inventors: Yi PEI, Haichun HUANG, Ming LEI, Han LI, Chi Shing SUM, Alla PRITSKER, Bor-Ruei LIN, Fangqiang TANG
  • Publication number: 20230396185
    Abstract: The present disclosure discloses a dual output energy conversion device, modulation method, and power supply device which can enhance the bus voltage boosting capability of the conversion device by using a first electric energy storage module, so that it can be used in a wider input voltage range. A first conversion output circuit and a second conversion output circuit are set, and voltage stress of all switching tubes is reduced to half of the direct current bus voltage, which can greatly reduce the system EMI of the conversion device in high-frequency applications, and improve the power conversion efficiency of the device. The dual output energy conversion device only needs to realize the control of one-stage power conversion, and has a simple control structure.
    Type: Application
    Filed: October 28, 2021
    Publication date: December 7, 2023
    Inventors: Mao HU, Yi PEI
  • Publication number: 20230331867
    Abstract: The present disclosure provides antibodies and antibody fragments thereof that bind to Nectin-4. Such antibodies and antibody fragments are useful for the treatment of cancer, either alone or in combination with other agents.
    Type: Application
    Filed: September 3, 2021
    Publication date: October 19, 2023
    Inventors: Yi PEI, Haichun HUANG, Ming LEI, Han LI
  • Publication number: 20230272063
    Abstract: Antibodies that specifically bind to the human tight junction molecule CLDN18.2 and have functional properties that make them suitable for use in antibody-based immunotherapies of a disease associated with aberrant expression of CLDN18.2 are disclosed.
    Type: Application
    Filed: July 13, 2022
    Publication date: August 31, 2023
    Inventors: Han Li, Ming Lei, Yi Pei, Haichun Huang
  • Publication number: 20230178616
    Abstract: Embodiments of the present disclosure disclose a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and a passive region, the semiconductor device further includes a substrate, a multilayer semiconductor layer, and a source, a gate and a drain, the gate being located between the source and the drain, wherein, in a first direction, the gate includes, in turn, a first end portion, an intermediate portion and a second end portion, the intermediate portion, the source and the drain all being located in the active region, and the first end portion and/or the second end portion extending into the passive region, and in a second direction, an extension width of a portion at least located in the passive region of the first end portion and/or the second end portion is greater than an extension width of the intermediate portion.
    Type: Application
    Filed: March 24, 2021
    Publication date: June 8, 2023
    Inventors: Naiqian ZHANG, Yi PEI