Abstract: The embodiments of the present invention disclose a high electron mobility transistor, comprising: a substrate; a channel layer located on the substrate; a barrier layer located on the channel layer; a source electrode, a drain electrode, and a schottky gate electrode located between the source electrode and the drain electrode, all located on the barrier layer; and at least one semiconductor field ring located on the barrier layer and between the schottky gate electrode and the drain electrode. In the embodiments of the present invention, a concentration of two-dimensional electron gas at an interface between a barrier layer and a channel layer can be adjusted. Therefore, the concentration effect of the electric field at an edge of a gate is effectively improved, and the breakdown voltage of high electron mobility transistors is increased.

Abstract: A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.

Abstract: A semiconductor device comprises an active region and a passive region located outside the active region. The active region comprises a plurality of active region units. At least one pair of adjacent active region units do not completely overlap in a length direction of the semiconductor device.

Abstract: A semiconductor device comprises: a substrate; a multilayer semiconductor layer located on the substrate; a source located on the multilayer semiconductor layer, the source including a first source portion inside an active region and a second source portion inside a passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion.

Abstract: A semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween.

Abstract: An enhancement mode high electron mobility transistor according to an embodiment of the present invention includes: a substrate; a channel layer, prepared above the substrate; a barrier layer, prepared above the channel layer; the barrier layer and the channel layer forming a heterojunction structure, and two dimensional electron gas being formed at an interface between the barrier layer and the channel layer; a groove, prepared inside the barrier layer; a semiconductor epitaxial layer, prepared above the groove by secondary growth; an in-situ dielectric layer, prepared above the semiconductor epitaxial layer; a gate electrode, prepared above the in-situ dielectric layer; a source electrode, prepared above the barrier layer; and a drain electrode, prepared above the barrier layer.

Abstract: A semiconductor device comprises: a substrate; a multilayer semiconductor layer located on the substrate; a source located on the multilayer semiconductor layer, the source including a first source portion inside an active region and a second source portion inside a passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion.

Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.

Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.

Abstract: The invention provides a novel truncated mutated T4 RNA ligase 2. In addition, methods are provided for ligating pre-adenlylated donor molecules to the 3? hydroxyl group of RNA in the absence of ATP using the ligase.

Abstract: The invention provides a novel truncated mutated T4 RNA ligase 2. In addition, methods are provided for ligating pre-adenlylated donor molecules to the 3? hydroxyl group of RNA in the absence of ATP using the ligase.

Abstract: The invention provides a novel truncated mutated T4 RNA ligase 2. In addition, methods are provided for ligating pre-adenlylated donor molecules to the 3? hydroxyl group of RNA in the absence of ATP using the ligase.

Abstract: The invention provides a novel truncated mutated T4 RNA ligase 2. In addition, methods are provided for ligating pre-adenlylated donor molecules to the 3? hydroxyl group of RNA in the absence of ATP using the ligase.

Abstract: The invention provides a novel truncated mutated T4 RNA ligase 2. In addition, methods are provided for ligating pre-adenlylated donor molecules to the 3? hydroxyl group of RNA in the absence of ATP using the ligase.

Abstract: A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.

Abstract: Cholesterol inhibitor produced by Monascus, monacolin k, is a secondary metabolite of polyketides. The invention provides probes specific to monacolin k biosynthesis gene cluster. BAC clones having putative monacolin k gene cluster were screened from BAC (bacterial artificial chromosome) library, and sequencing and annotation were performed on these clones. The results show that 2 polyketide synthase (PKS) genes and 7 regulatory genes related to monacolin k synthesis were obtained. Full-length cDNAs of these genes were then obtained by RT-PCR and cloned to expression vectors for the expression of these genes.

Abstract: Retrotransposons and methods related thereto. The retrotransposon comprises a nucleotide sequence selected from a group consisting of a nucleotide sequence of SEQ ID NO: 1, a nucleotide sequence of SEQ ID NO: 2, a nucleotide sequence of SEQ ID NO: 3, and a nucleotide sequence encoding a polypeptide of an amino acid sequence of SEQ ID NO: 4.

Abstract: A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.

Abstract: A convertible mattress and bedding system includes first and second bed frames and first and second mattresses. At least one of the bed frames is laterally moveable relative to the other of the bed frames from a one bed configuration to a two bed configuration. Each mattress includes first and second longitudinally extending mattress halves. The first mattress half is connected to the second mattress half by a longitudinally extending hinge and is movable from a folded condition, with the first mattress half disposed above the second mattress half, to an open condition, with the first mattress half disposed laterally adjacent the second mattress half. The first mattress is disposed on the first bed frame in a folded condition and the second mattress is disposed on the second bed frame in a folded condition when the bed frames are in the two bed configuration.

Abstract: Retrotransposons and methods related thereto. The retrotransposon comprises a nucleotide sequence selected from a group consisting of a nucleotide sequence of SEQ ID NO: 1, a nucleotide sequence of SEQ ID NO: 2, a nucleotide sequence of SEQ ID NO: 3, and a nucleotide sequence encoding a polypeptide of an amino acid sequence of SEQ ID NO: 4.