Patents by Inventor Yi Pei

Yi Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10749005
    Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. A semiconductor device according to a performing mode includes a substrate, a semiconductor layer located on one side of the substrate, a source and a drain located on one side of the semiconductor layer away from the substrate, and a gate located between the source and the drain, and an isolation structure disposed on one side of the semiconductor layer away from the substrate, one end of the isolation structure being disposed at a side close to the source, and the other end being disposed at a side close to the drain and in direct contact with the surface layer of the semiconductor device, the isolation structure covering the gate or a part of the gate, the isolation structure being an integrally formed structure and forming a chamber with the semiconductor layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: August 18, 2020
    Assignee: DYNAX SEMICONDUCTOR, INC.
    Inventors: Yi Pei, Feihang Liu
  • Patent number: 10686063
    Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor layer, a source and a drain located on one side of the semiconductor layer, a blocking layer located on one side of the semiconductor layer, the blocking layer including silicide, wherein the distance between an interface at one side of the blocking layer close to the semiconductor layer and the semiconductor layer is equal to or more than 10 nm, and a gate located between the source and the drain, the gate penetrating through the blocking layer, the gate including a first conductive layer and a second conductive layer, the first conductive layer being close to the semiconductor layer, the second conductive layer being located on one side of the first conductive layer away from the semiconductor layer, and the first conductive layer including nickel.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 16, 2020
    Assignee: DYNAX SEMICONDUCTOR, INC.
    Inventors: Yi Pei, Chenggong Yin
  • Patent number: 10683487
    Abstract: A Myrmecridium flexuosum NUK-21, a novel lactose oxidase isolated from the Myrmecridium flexuosum NUK-21 and a method for conversion of lactose into lactobionic acid (LBA) by the novel lactose oxidase are disclosed herein. The Myrmecridium flexuosum NUK-21 produces high yields of the novel lactose oxidase and the novel lactose oxidase has higher reactivity and specificity of converting lactose into lactobionic acid.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 16, 2020
    Assignee: National University of Kaohsiung
    Inventors: Shuen-Fuh Lin, Cheng-Ke Li, Yi-Pei Chung
  • Patent number: 10672917
    Abstract: The present disclosure provides a schottky barrier rectifier, comprising: a communication layer; a drift layer provided on a side of the communication layer and forming a heterojunction structure together with the communication layer; anode metal provided on a side of the drift layer away from the communication layer; and cathode metal provided on a side of the communication layer away from the drift layer. The drift layer is provided with a first area, which extends in a direction of thickness thereof, between a surface of the drift layer away from the communication layer and a surface thereof close to the communication layer, the first are a containing a first metal element and the content of the first metal element in the first area changing in the direction of thickness. The rectifier of the present disclosure uses polarized charges formed by a heterojunction, and thus the breakdown voltage of devices may be improved.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 2, 2020
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Yi Pei, Qiang Liu
  • Publication number: 20200058573
    Abstract: The present disclosure provides a heat dissipation structure of a semiconductor device and a semiconductor device, and it relates to a field of semiconductor technology. A heat dissipation structure of a semiconductor device according to an embodiment includes a first heat dissipation window formed on an upper surface of the heat dissipation structure at a side close to the semiconductor device, and at least one heat dissipation channel, the heat dissipation channel including an inflow channel and an outflow channel, transmitting a heat conducting medium to the first heat dissipation window via the inflow channel, the inflow channel including a first opening and a second opening, wherein the first opening is away from the first heat dissipation window, the second opening is close to the first heat dissipation window, and an opening area of the first opening is greater than an opening area of the second opening.
    Type: Application
    Filed: August 7, 2018
    Publication date: February 20, 2020
    Inventors: Chuanjia WU, Yi PEI
  • Patent number: 10439029
    Abstract: A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, and the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 8, 2019
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Yuan Li, Yi Pei, Feihang Liu
  • Publication number: 20190271737
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same, and relates to the field of semiconductor devices. The semiconductor device includes an active region, a test region and a passive region located outside the active region and the test region, wherein a standard device is formed in the active region, and a test device for testing performance parameters of the standard device is formed in the test region.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 5, 2019
    Inventors: Naiqian ZHANG, Jian LIU, Feihang LIU, Yi PEI
  • Patent number: 10361271
    Abstract: A semiconductor device comprises an active region and a passive region located outside the active region. The active region comprises a plurality of active region units. At least one pair of adjacent active region units do not completely overlap in a length direction of the semiconductor device.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 23, 2019
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Naiqian Zhang, Feihang Liu, Yi Pei
  • Patent number: 10312176
    Abstract: A semiconductor device comprises: a substrate; a multi-layer semiconductor layer located on the substrate, the multi-layer semiconductor layer being divided into an active area and a passive area outside the active area; a gate electrode, a source electrode and a drain electrode all located on the multi-layer semiconductor layer and within the active area; and a heat dissipation layer covering at least one portion of the active area and containing a heat dissipation material. In embodiments of the present invention, a heat dissipation layer covering at least one portion of the active area is provided in the semiconductor device. The arrangement of the heat dissipation layer adds a heat dissipation approach for the semiconductor device in the planar direction, thus the heat dissipation effect of the semiconductor device is improved.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 4, 2019
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Yi Pei, Mengjie Zhou
  • Publication number: 20190127709
    Abstract: A Myrmecridium flexuosum NUK-21, a novel lactose oxidase isolated from the Myrmecridium flexuosum NUK-21 and a method for conversion of lactose into lactobionic acid (LBA) by the novel lactose oxidase are disclosed herein. The Myrmecridium flexuosum NUK-21 produces high yields of the novel lactose oxidase and the novel lactose oxidase has higher reactivity and specificity of converting lactose into lactobionic acid.
    Type: Application
    Filed: September 4, 2018
    Publication date: May 2, 2019
    Inventors: SHUEN-FUH LIN, CHENG-KE LI, YI-PEI CHUNG
  • Patent number: 10256333
    Abstract: The embodiments of the present invention disclose a high electron mobility transistor, comprising: a substrate; a channel layer located on the substrate; a barrier layer located on the channel layer; a source electrode, a drain electrode, and a schottky gate electrode located between the source electrode and the drain electrode, all located on the barrier layer; and at least one semiconductor field ring located on the barrier layer and between the schottky gate electrode and the drain electrode. In the embodiments of the present invention, a concentration of two-dimensional electron gas at an interface between a barrier layer and a channel layer can be adjusted. Therefore, the concentration effect of the electric field at an edge of a gate is effectively improved, and the breakdown voltage of high electron mobility transistors is increased.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: April 9, 2019
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventor: Yi Pei
  • Publication number: 20190043977
    Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor layer, a source and a drain located on one side of the semiconductor layer, a blocking layer located on one side of the semiconductor layer, the blocking layer including silicide, wherein the distance between an interface at one side of the blocking layer close to the semiconductor layer and the semiconductor layer is equal to or more than 10 nm, and a gate located between the source and the drain, the gate penetrating through the blocking layer, the gate including a first conductive layer and a second conductive layer, the first conductive layer being close to the semiconductor layer, the second conductive layer being located on one side of the first conductive layer away from the semiconductor layer, and the first conductive layer including nickel.
    Type: Application
    Filed: April 13, 2018
    Publication date: February 7, 2019
    Inventors: Yi PEI, Chenggong YIN
  • Publication number: 20180337239
    Abstract: A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, and the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.
    Type: Application
    Filed: August 1, 2018
    Publication date: November 22, 2018
    Inventors: Yuan LI, Yi PEI, Feihang LIU
  • Publication number: 20180331235
    Abstract: A Schottky diode comprises: a semiconductor layer and a three-terminal port located on a side of the semiconductor layer; the three-terminal port comprises a first electrode, a second electrode, and a third electrode located between the first electrode and the second electrode, at least a part of the second electrode extends into the semiconductor layer and forms a Schottky contact with the semiconductor layer, the second electrode and the third electrode are electrically connected to form an anode of the Schottky diode, and the first electrode is in ohmic contact with the semiconductor layer as a cathode of the Schottky diode; when the Schottky diode is subjected to a reverse bias voltage, a depletion layer is formed under the third electrode.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 15, 2018
    Inventors: Yi PEI, Xiaoyan PEI
  • Patent number: 10103219
    Abstract: The present disclosure discloses a power semiconductor device and a method for manufacturing the same. The power semiconductor device comprises: a substrate, a channel layer, a barrier layer, a source electrode, a drain electrode, a gate electrode, and a junction termination structure located on the barrier layer. The power semiconductor device extends in a first direction from an edge of a side of the gate electrode close to the drain electrode to the drain electrode, the junction termination structure at least comprises a first region close to the gate electrode and a second region away from the gate electrode and the thickness of the first region is greater than that of the second region in a second direction perpendicular to the barrier layer. The junction termination structure can effectively improve the distribution of an electric field of the barrier layer and hence increase the breakdown voltage of the device.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 16, 2018
    Assignee: Gpower Semiconductor, Inc.
    Inventors: Yi Pei, Yuan Li, Chuanjia Wu
  • Patent number: 10068974
    Abstract: A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.
    Type: Grant
    Filed: February 25, 2017
    Date of Patent: September 4, 2018
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Yuan Li, Yi Pei, Feihang Liu
  • Publication number: 20180158965
    Abstract: The present disclosure provides a schottky barrier rectifier, comprising: a communication layer; a drift layer provided on a side of the communication layer and forming a heterojunction structure together with the communication layer; anode metal provided on a side of the drift layer away from the communication layer; and cathode metal provided on a side of the communication layer away from the drift layer. The drift layer is provided with a first area, which extends in a direction of thickness thereof, between a surface of the drift layer away from the communication layer and a surface thereof close to the communication layer, the first are a containing a first metal element and the content of the first metal element in the first area changing in the direction of thickness. The rectifier of the present disclosure uses polarized charges formed by a heterojunction, and thus the breakdown voltage of devices may be improved.
    Type: Application
    Filed: June 29, 2017
    Publication date: June 7, 2018
    Inventors: Yi PEI, Qiang LIU
  • Publication number: 20180138305
    Abstract: A semiconductor device comprises: a substrate; a semiconductor layer on the substrate; and a gallium nitride cap layer on the semiconductor layer. The gallium nitride cap layer has a thickness of 3 nm to 5.8 nm.
    Type: Application
    Filed: January 23, 2017
    Publication date: May 17, 2018
    Inventors: Guangmin DENG, Yi PEI
  • Publication number: 20170287811
    Abstract: A semiconductor device comprises: a substrate; a multi-layer semiconductor layer located on the substrate, the multi-layer semiconductor layer being divided into an active area and a passive area outside the active area; a gate electrode, a source electrode and a drain electrode all located on the multi-layer semiconductor layer and within the active area; and a heat dissipation layer covering at least one portion of the active area and containing a heat dissipation material. In embodiments of the present invention, a heat dissipation layer covering at least one portion of the active area is provided in the semiconductor device. The arrangement of the heat dissipation layer adds a heat dissipation approach for the semiconductor device in the planar direction, thus the heat dissipation effect of the semiconductor device is improved.
    Type: Application
    Filed: April 3, 2017
    Publication date: October 5, 2017
    Inventors: Yi PEI, Mengjie ZHOU
  • Publication number: 20170207300
    Abstract: The present disclosure discloses a power semiconductor device and a method for manufacturing the same. The power semiconductor device comprises: a substrate, a channel layer, a barrier layer, a source electrode, a drain electrode, a gate electrode, and a junction termination structure located on the barrier layer. The power semiconductor device extends in a first direction from an edge of a side of the gate electrode close to the drain electrode to the drain electrode, the junction termination structure at least comprises a first region close to the gate electrode and a second region away from the gate electrode and the thickness of the first region is greater than that of the second region in a second direction perpendicular to the barrier layer. The junction termination structure can effectively improve the distribution of an electric field of the barrier layer and hence increase the breakdown voltage of the device.
    Type: Application
    Filed: March 29, 2017
    Publication date: July 20, 2017
    Inventors: Yi PEI, Yuan LI, Chuanjia WU