Abstract: A Myrmecridium flexuosum NUK-21, a novel lactose oxidase isolated from the Myrmecridium flexuosum NUK-21 and a method for conversion of lactose into lactobionic acid (LBA) by the novel lactose oxidase are disclosed herein. The Myrmecridium flexuosum NUK-21 produces high yields of the novel lactose oxidase and the novel lactose oxidase has higher reactivity and specificity of converting lactose into lactobionic acid.

Abstract: The embodiments of the present invention disclose a high electron mobility transistor, comprising: a substrate; a channel layer located on the substrate; a barrier layer located on the channel layer; a source electrode, a drain electrode, and a schottky gate electrode located between the source electrode and the drain electrode, all located on the barrier layer; and at least one semiconductor field ring located on the barrier layer and between the schottky gate electrode and the drain electrode. In the embodiments of the present invention, a concentration of two-dimensional electron gas at an interface between a barrier layer and a channel layer can be adjusted. Therefore, the concentration effect of the electric field at an edge of a gate is effectively improved, and the breakdown voltage of high electron mobility transistors is increased.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor layer, a source and a drain located on one side of the semiconductor layer, a blocking layer located on one side of the semiconductor layer, the blocking layer including silicide, wherein the distance between an interface at one side of the blocking layer close to the semiconductor layer and the semiconductor layer is equal to or more than 10 nm, and a gate located between the source and the drain, the gate penetrating through the blocking layer, the gate including a first conductive layer and a second conductive layer, the first conductive layer being close to the semiconductor layer, the second conductive layer being located on one side of the first conductive layer away from the semiconductor layer, and the first conductive layer including nickel.

Abstract: A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, and the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.

Abstract: A Schottky diode comprises: a semiconductor layer and a three-terminal port located on a side of the semiconductor layer; the three-terminal port comprises a first electrode, a second electrode, and a third electrode located between the first electrode and the second electrode, at least a part of the second electrode extends into the semiconductor layer and forms a Schottky contact with the semiconductor layer, the second electrode and the third electrode are electrically connected to form an anode of the Schottky diode, and the first electrode is in ohmic contact with the semiconductor layer as a cathode of the Schottky diode; when the Schottky diode is subjected to a reverse bias voltage, a depletion layer is formed under the third electrode.

Abstract: The present disclosure discloses a power semiconductor device and a method for manufacturing the same. The power semiconductor device comprises: a substrate, a channel layer, a barrier layer, a source electrode, a drain electrode, a gate electrode, and a junction termination structure located on the barrier layer. The power semiconductor device extends in a first direction from an edge of a side of the gate electrode close to the drain electrode to the drain electrode, the junction termination structure at least comprises a first region close to the gate electrode and a second region away from the gate electrode and the thickness of the first region is greater than that of the second region in a second direction perpendicular to the barrier layer. The junction termination structure can effectively improve the distribution of an electric field of the barrier layer and hence increase the breakdown voltage of the device.

Abstract: A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.

Abstract: The present disclosure provides a schottky barrier rectifier, comprising: a communication layer; a drift layer provided on a side of the communication layer and forming a heterojunction structure together with the communication layer; anode metal provided on a side of the drift layer away from the communication layer; and cathode metal provided on a side of the communication layer away from the drift layer. The drift layer is provided with a first area, which extends in a direction of thickness thereof, between a surface of the drift layer away from the communication layer and a surface thereof close to the communication layer, the first are a containing a first metal element and the content of the first metal element in the first area changing in the direction of thickness. The rectifier of the present disclosure uses polarized charges formed by a heterojunction, and thus the breakdown voltage of devices may be improved.

Abstract: A semiconductor device comprises: a substrate; a semiconductor layer on the substrate; and a gallium nitride cap layer on the semiconductor layer. The gallium nitride cap layer has a thickness of 3 nm to 5.8 nm.

Abstract: A semiconductor device comprises: a substrate; a multi-layer semiconductor layer located on the substrate, the multi-layer semiconductor layer being divided into an active area and a passive area outside the active area; a gate electrode, a source electrode and a drain electrode all located on the multi-layer semiconductor layer and within the active area; and a heat dissipation layer covering at least one portion of the active area and containing a heat dissipation material. In embodiments of the present invention, a heat dissipation layer covering at least one portion of the active area is provided in the semiconductor device. The arrangement of the heat dissipation layer adds a heat dissipation approach for the semiconductor device in the planar direction, thus the heat dissipation effect of the semiconductor device is improved.

Abstract: The present disclosure discloses a power semiconductor device and a method for manufacturing the same. The power semiconductor device comprises: a substrate, a channel layer, a barrier layer, a source electrode, a drain electrode, a gate electrode, and a junction termination structure located on the barrier layer. The power semiconductor device extends in a first direction from an edge of a side of the gate electrode close to the drain electrode to the drain electrode, the junction termination structure at least comprises a first region close to the gate electrode and a second region away from the gate electrode and the thickness of the first region is greater than that of the second region in a second direction perpendicular to the barrier layer. The junction termination structure can effectively improve the distribution of an electric field of the barrier layer and hence increase the breakdown voltage of the device.

Abstract: The embodiments of the present invention disclose a high electron mobility transistor, comprising: a substrate; a channel layer located on the substrate; a barrier layer located on the channel layer; a source electrode, a drain electrode, and a schottky gate electrode located between the source electrode and the drain electrode, all located on the barrier layer; and at least one semiconductor field ring located on the barrier layer and between the schottky gate electrode and the drain electrode. In the embodiments of the present invention, a concentration of two-dimensional electron gas at an interface between a barrier layer and a channel layer can be adjusted. Therefore, the concentration effect of the electric field at an edge of a gate is effectively improved, and the breakdown voltage of high electron mobility transistors is increased.

Abstract: A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.

Abstract: A semiconductor device comprises an active region and a passive region located outside the active region. The active region comprises a plurality of active region units. At least one pair of adjacent active region units do not completely overlap in a length direction of the semiconductor device.

Abstract: A semiconductor device comprises: a substrate; a multilayer semiconductor layer located on the substrate; a source located on the multilayer semiconductor layer, the source including a first source portion inside an active region and a second source portion inside a passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion.

Abstract: A semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween.

Abstract: An enhancement mode high electron mobility transistor according to an embodiment of the present invention includes: a substrate; a channel layer, prepared above the substrate; a barrier layer, prepared above the channel layer; the barrier layer and the channel layer forming a heterojunction structure, and two dimensional electron gas being formed at an interface between the barrier layer and the channel layer; a groove, prepared inside the barrier layer; a semiconductor epitaxial layer, prepared above the groove by secondary growth; an in-situ dielectric layer, prepared above the semiconductor epitaxial layer; a gate electrode, prepared above the in-situ dielectric layer; a source electrode, prepared above the barrier layer; and a drain electrode, prepared above the barrier layer.

Abstract: A semiconductor device comprises: a substrate; a multilayer semiconductor layer located on the substrate; a source located on the multilayer semiconductor layer, the source including a first source portion inside an active region and a second source portion inside a passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion.

Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.

Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.