Patents by Inventor Yi Su

Yi Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9620498
    Abstract: A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend.
    Type: Grant
    Filed: July 26, 2014
    Date of Patent: April 11, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yi Su, Anup Bhalla, Daniel Ng
  • Patent number: 9620934
    Abstract: A known flip-chip assembly manufacturing process is augmented by process steps of the invention to create a VCSEL flip-chip assembly comprising a plurality of semiconductor devices having respective arrays of a small number of VCSELs thereon, which are mounted on a substrate to form a large array of VCSELs that are precisely optically aligned with their respective optical coupling elements.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: April 11, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Chung-Yi Su, Tak K. Wang
  • Patent number: 9620421
    Abstract: A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: April 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Ho, Chih-Ping Chao, Hua-Chou Tseng, Chun-Hung Chen, Chia-Yi Su, Alex Kalnitsky, Jye-Yen Cheng, Harry-Hak-Lay Chuang
  • Publication number: 20170097480
    Abstract: A constructed photodetector, an optical receiver, and a receiver unit in an optical communication system are disclosed. One example of the disclosed constructed photodetector includes an optoelectronic element having an active area that converts light having a wavelength of interest into electrical signals and a substrate on a face that opposes the active area, where the substrate is non-transparent to light having the wavelength of interest. The constructed photodetector further includes a lens-chip that is at least partially transparent to light having the wavelength of interest, where the lens-chip includes a first side and an opposing second side, where the first side of the lens-chip includes an integrated lens, and where the second side of the lens-chip includes one or more electrical traces. The constructed photodetector further includes at least one connector that provides a physical and electrical connection between the optoelectronic element and the lens-chip.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: Tak Kui Wang, Ye Chen, Chung-Yi Su, Frank Yashar
  • Patent number: 9611394
    Abstract: A floor board includes a board unit that includes a substrate and a coating unit. The substrate has a first side surface, a second side surface opposite to the first side surface, a male engaging part extending outwardly from the first side surface, and a female engaging part indented inwardly from the second side surface. The male engaging part corresponds in shape to the female engaging part. The coating unit is formed on the first and second side surfaces, and the male and female engaging parts, and includes a far-infrared radiating material.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 4, 2017
    Inventor: Cheng-Yi Su
  • Publication number: 20170063040
    Abstract: A vertical cavity surface emitting laser (VCSEL) includes a substrate having an aperture that allows light generated in an active layer of the VCSEL to exit the VCSEL after propagation through a first set of semiconductor layers. The VCSEL further includes an opaque bottom layer that blocks light generated in the active layer and propagated through a second set of semiconductor layers. The opaque bottom layer can be attached to a heat sink for heat dissipation thereby allowing the VCSEL to be operated at high power levels. The active layer is sandwiched between the first set of semiconductor layers and the second set of semiconductor layers. Unlike a traditional VCSEL where only certain wavelengths of light can propagate through a solid substrate that is “transparent” to these particular wavelengths, the aperture provided in the substrate of a VCSEL in accordance with the disclosure allows for propagation of many different wavelengths.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Chung-Yi Su, Christine Chen
  • Publication number: 20170063035
    Abstract: A wafer-to-wafer bonded arrangement is provided comprising a VCSEL wafer and a highly thermally-conductive (HTC) wafer that are bonded together with the front side of the VCSEL wafer bonded to the HTC wafer. The VCSEL wafer is fabricated to include, at least initially, a native substrate. The HTC wafer includes a thermally-conductive, non-native substrate. All or a portion of the native substrate may be removed after performing wafer-to-wafer bonding. In effect, the HTC wafer becomes the substrate of the bonded pair. During operation of VCSEL dies diced from the bonded wafer, heat generated by the dies flows into the non-native substrate where the heat spreads out and is dissipated. Laser light generated by the VCSEL die is emitted through the back side of the VCSEL die.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Tak Kui Wang, Chung-Yi Su
  • Publication number: 20170017741
    Abstract: A computational engineering modelling tool having a point generation module arranged to read geometry data representing a domain to be modelled. The point generation module also generates point data for the domain having multiple boundary points located on a boundary of the domain and multiple further points spaced from the boundary within the domain. A point mutation module processes the point generation module output and generates automatically a plurality of alternative point data definitions for the domain in which the location of at least one point differs between each of the alternative point definitions. A blocking module discretizes the domain by creating multiple geometric blocks over the domain using a computational geometric operator wherein each point represents a vertex of at least one block. The blocking module outputs a discretized computational model of the domain and the tool scores the model according to a geometric attribute of the blocks.
    Type: Application
    Filed: July 6, 2016
    Publication date: January 19, 2017
    Applicant: ROLLS-ROYCE plc
    Inventors: Chi Wan LIM, Xiaofeng YIN, Tianyou ZHANG, Yi SU, Chi-Keong GOH, Shahrokh SHAHPAR, Alejandro MORENO
  • Patent number: 9511024
    Abstract: The present invention provides new amino lipids and a convenient method for synthesizing these compounds. These (cationic) amino lipids have good properties as transfection agents. The method is an economic versatile two step synthesis allowing the preparation of various amino lipids thus leading to the assembly of a combinatorial library of transfection agents. Moreover, the present invention provides lipid particles (liposomes) containing said amino lipids and their use for delivering bioactive agents into cells. The invention encompasses also the use of lipid particles containing the cationic amino lipids as medicament.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: December 6, 2016
    Assignee: INCELLA GMBH
    Inventors: Gary Davidson, Pavel Levkin, Linxian Li, Yi Su, David Zahner
  • Publication number: 20160351683
    Abstract: A channel layer is grown over a substrate, and an active layer is grown over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A dielectric layer is deposited over the active layer, and the dielectric layer is patterned to expose a portion of the active layer. A metal diffusion barrier is formed over the exposed portion of the active layer, and a gate is deposited over the metal diffusion barrier.
    Type: Application
    Filed: August 10, 2016
    Publication date: December 1, 2016
    Inventors: King-Yuen WONG, Po-Chih CHEN, Chen-Ju YU, Fu-Chih YANG, Jiun-Lei Jerry YU, Fu-Wei YAO, Ru-Yi SU, Yu-Syuan LIN
  • Patent number: 9508140
    Abstract: A method and system are proposed to obtain quantitative data about the shape of a biological structure, and especially a heart ventricle. A set of three-dimensional input meshes are generated from MRI data. They represent the shape of a ventricle at successive times. The input meshes are used to generate a set of three-dimensional morphed meshes which have the same number of vertices as each other, and have respective shapes which are the shapes of corresponding ones of the input meshes. Then, for each of the times, shape analysis is performed to obtain a curvedness value at each of a plurality of corresponding locations in the morphed meshes. The curvedness value may be used to obtain a curvedness rate at each of the locations, indicative of the rate of change of curvedness with time at each of the locations.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: November 29, 2016
    Assignees: Agency for Science, Technology and Research, Singapore Health Services Pte Ltd
    Inventors: Yi Su, Chi Wan Calvin Lim, Ru San Tan, Liang Zhong
  • Publication number: 20160340513
    Abstract: A floor board includes a board unit that includes a substrate and a coating unit. The substrate has a first side surface, a second side surface opposite to the first side surface, a male engaging part extending outwardly from the first side surface, and a female engaging part indented inwardly from the second side surface. The male engaging part corresponds in shape to the female engaging part. The coating unit is formed on the first and second side surfaces, and the male and female engaging parts, and includes a far-infrared radiating material.
    Type: Application
    Filed: May 10, 2016
    Publication date: November 24, 2016
    Inventor: Cheng-Yi Su
  • Publication number: 20160315694
    Abstract: The present disclosure describes a method and an apparatus for pruning false peaks during slot synchronization at a user equipment (UE). For example, a method is provided to identify a plurality of first peaks associated with a primary-synchronization channel (P-SCH) received at the UE and a plurality of second peaks from the plurality of first peaks. Further, one or more pruning locations along with associated energy thresholds for each of the plurality of the second peaks may be determined and whether a peak of the plurality of the first peaks is a false peak is identified based on whether the peak is located at one of the one or more pruning locations of the peak and an associated energy value of the peak does not satisfy the associated energy threshold of the pruning location. Furthermore, the peak identified as the false peak is discarded.
    Type: Application
    Filed: January 15, 2016
    Publication date: October 27, 2016
    Inventors: Shashank MAIYA, Yi SU, Harish VENKATACHARI, Nate CHIZGI
  • Publication number: 20160308036
    Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), and more particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventors: Ker-Hsiao Huo, Fu-Chih Yang, Jen-Hao Yeh, Chun Lin Tsai, Chih-Chang Cheng, Ru-Yi Su
  • Publication number: 20160293696
    Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 6, 2016
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Publication number: 20160293694
    Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.
    Type: Application
    Filed: June 17, 2016
    Publication date: October 6, 2016
    Inventors: Ru-Yi SU, Fu-Chih YANG, Chun Lin TSAI, Chih-Chang CHENG, Ruey-Hsin LIU
  • Publication number: 20160291270
    Abstract: An optical communications system and a pluggable optical communications module for use in the system are provided. The configuration of the pluggable optical communications module is such that no optical turn in any light path is required. Embodiments of the optical communications module include an EMI shielding solution and an electrical interface for electrically interfacing an electrical subassembly (ESA) of the module with a system printed circuit board (PCB) in a way that obviates the need for an optical turn.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 6, 2016
    Inventors: Tak Kui Wang, Chung-Yi Su
  • Publication number: 20160279251
    Abstract: Provided herein are particles assemblies including a shell surrounding a core. The shell includes a particle-stabilizing random copolymer. The core includes a core random copolymer. The particle assemblies have a biomimetic design in which the polymeric components containing discrete chemical and biological functionalities are designed to spontaneously self-assemble into particles. Also provided herein are random copolymers having conjugated therapeutic agents that can be cleaved from the copolymers by an enzyme or water.
    Type: Application
    Filed: November 12, 2014
    Publication date: September 29, 2016
    Applicant: University of Washington through its Center for Commercialization
    Inventors: Patrick S. Stayton, Anthony Convertine, Daniel M. Ratner, Selvi Srinivasan, Debobrato Das, Fang-Yi Su, Jasmin Chen, David Yee-Shawn Chiu, Daniel Douglas Lane
  • Patent number: 9443969
    Abstract: A transistor includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a metal diffusion barrier over the active layer, and a gate over the metal diffusion barrier. The active layer has a band gap discontinuity with the channel layer.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: September 13, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: King-Yuen Wong, Po-Chih Chen, Chen-Ju Yu, Fu-Chih Yang, Jiun-Lei Jerry Yu, Fu-Wei Yao, Ru-Yi Su, Yu-Syuan Lin
  • Patent number: 9432918
    Abstract: Apparatus and methods of receive diversity (RxD) full cell search by a user equipment (UE) in a wireless communication system are described. In an aspect, a first set of received energies of a first signal received at a first antenna and a second set of received energies of a second signal received at a second antenna may be separately determined. Based thereon, a set of peak energies and corresponding antenna indices, along with a slot timing of at least one cell corresponding to the set of peak energies and corresponding antenna indices, may be determined. A frame timing and a scrambling code for the at least one cell then may be determined using a respective one of the first antenna and the second antenna corresponding to each of the set of peak energies and the corresponding antenna indices, along with the respective slot timing of the at least one cell.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: August 30, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Yi Su, Sharif Ahsanul Matin, Ahmad Bilal Hasan, Ramesh Chandra Chirala, Atin Kumar, An-Swol Clement Hu