Patents by Inventor Yi Su

Yi Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10237801
    Abstract: Cell reselection for transitioning a user device from a macro cell to a small cell may be performed by comparing a first reselection candidate small cell and a second reselection candidate small cell based on reselection criteria, and selecting a final reselection candidate based on the comparison.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: March 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Yi Su, Sundaresan Tambaram Kailasam, Feilu Liu, Yongle Wu, Joshua Tennyson MacDonald, Satish Pavan Kumar Nichanametla, Uzma Khan Qazi, Aziz Gholmieh, Scott Allan Hoover, Feng Lu
  • Patent number: 10235750
    Abstract: A method is proposed for identifying an anatomical structure within a spatial-temporal image (i.e. a series of frames captured as respective times). A current frame of spatial-temporal medical image is processed using information from one or more previous and/or subsequent temporal frames, to aid in the segmentation of an object or a region of interest (ROI) in a current frame. The invention is applicable to both two- and three-dimensional spatial-temporal images (i.e., 2D+time or 3D+time), and in particular to cardiac magnetic resonance (CMR images). An initialization process for this method segments the left ventricle (LV) in a CMR image by a fuzzy c-means (FCM) clustering algorithm which employs a circular shape function as part of the definition of the dissimilarity measure.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 19, 2019
    Assignees: Agency for Science, Technology and Research, Singapore Health Services Pte Ltd
    Inventors: Xulei Yang, Yi Su, Si Yong Yeo, Liang Zhong, Ru San Tan
  • Publication number: 20190071369
    Abstract: A ceramic and plastic composite and a method for fabricating the same are disclosed. A chemical cleaning treatment, a microetching treatment, a hole reaming treatment, and a surface activating treatment are performed on the surface of a ceramic matrix to form nanoholes with an average diameter ranging between 150 nm and 450 nm. Plastics are injected onto the surface of the baked ceramic matrix to form a plastic layer. The plastic layer more deeply fills the nanoholes to have higher adhesion. Thus, the higher combined strength and air tightness exist between the ceramic matrix and the plastic layer to improve the reliability and the using performance of the ceramic and plastic composite.
    Type: Application
    Filed: May 14, 2018
    Publication date: March 7, 2019
    Inventors: Wen-Tung CHANG, Jong-Yi SU
  • Publication number: 20190071323
    Abstract: A process to treat fines tailings generated from mining operations, wherein tailings material is sprayed onto a solid substrate as a thin layer and allowed to dry. The spray may be re-applied on top of the dried tailings film leading to multiple layers of dried tailings solids. The method may yield a solid, dry, and consolidated tailings material.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 7, 2019
    Inventors: Ian D. Gates, Jingyi Wang, Spencer Fried, Yi Su
  • Publication number: 20190067184
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Application
    Filed: October 25, 2018
    Publication date: February 28, 2019
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Patent number: 10214564
    Abstract: A pharmaceutical composition for use in killing and/or inhibiting the growth and/or proliferation of a microorganism in a subject in need thereof, or for treating a subject afflicted with a microbial infection is disclosed. The composition comprises: (a) an effective amount of an isolated peptide, wherein the peptide comprises the arginine-rich carboxy-terminal region of hepatitis B virus core protein (HBc) and exhibits an antimicrobial activity; and (b) a pharmaceutically acceptable carrier. The peptide exhibits an activity against Gram-negative bacteria, Gram-positive bacteria, and/or fungi.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: February 26, 2019
    Assignee: Academia Sinica
    Inventors: Chiaho Shih, Heng-Li Chen, Pei-Yi Su
  • Patent number: 10200918
    Abstract: The present disclosure provides a mechanism that may allow a UE to determine whether PBCH repetition is enabled in the target cell without performing a hypothesis test. For example, the apparatus may receive a handover message from a serving cell. In an aspect, the handover message may be associated with a handover procedure to a target cell. In addition, the apparatus may determine whether to perform a hypothesis test to determine if a PBCH repetition is enabled in the target cell based on the handover message. In one example, the apparatus may determine not to perform the hypothesis test when the handover message includes information that indicates if the PBCH repetition is enabled in the target cell. In another example, the apparatus may determine to perform the hypothesis test when the handover message does not include information that indicates if the PBCH repetition is enabled in the target cell.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: February 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Achaleshwar Sahai, Yi Su, Shashidhar Vummintala, Masato Kitazoe
  • Patent number: 10156688
    Abstract: A passive alignment system is provided that comprises one or more first meltable elements disposed on a surface, one or more second meltable elements disposed on a surface and one or more first standoff devices. The first and second meltable elements transition from first and second pre-molten states, respectively, to first and second molten states, respectively, when subjected to first and second temperatures, respectively. In the first molten state, the first meltable elements control relative alignment between the surfaces in first and second dimensions. In the second molten state, the second meltable elements and the first standoff devices control relative alignment between the surfaces in a third dimension. The passive alignment system is suitable for use in a parallel optical communications module to precisely passively align ends of a plurality of optical fibers or waveguides with respective light sources or light detectors of the module.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: December 18, 2018
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Tak Kui Wang, Chung-Yi Su
  • Publication number: 20180358433
    Abstract: Aspects of the present disclosure disclose a superjunction trench MOSFET device for low voltage or medium voltage devices and a method of fabricating the same. The superjunction trench MOSFET device according to aspects of the present disclosure comprises an active cell region and a termination region disposed at an outer periphery of the active cell region. The active cell region comprises an array of device cells with the superjunction structure. The termination region may comprise a termination structure. In one embodiment, the termination structure includes guard rings in an intrinsic epitaxial layer. In one embodiment, the termination structure includes an array of floating P columns. In another embodiment, the termination structure includes an array of floating P columns and floating termination trenches.
    Type: Application
    Filed: June 12, 2017
    Publication date: December 13, 2018
    Inventors: Yi Su, Sik Lui
  • Patent number: 10153231
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Patent number: 10147844
    Abstract: A quantum dot includes: a core including at least one first positive ion precursor and at least one negative ion precursor; a shell including at least one second positive ion precursor and at least one negative ion precursor and wrapping the core; and a ligand formed on a surface of the shell, wherein the first positive ion precursor is an n-period element and the second positive ion precursor is an (n-1)-period element, where n is an integer of 3 to 6.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 4, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong Chan Kim, Yoon Hyeung Cho, Yi Su Kim
  • Publication number: 20180323273
    Abstract: In one general aspect, a device can include a first trench disposed in a semiconductor region, a second trench disposed in the semiconductor region, and a recess disposed in the semiconductor region between the first trench and the second trench. The recess has a sidewall and a bottom surface. The device also includes a Schottky interface along a sidewall of the recess and the bottom surface of the recess excludes a Schottky interface.
    Type: Application
    Filed: May 3, 2017
    Publication date: November 8, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yi SU, Ashok CHALLA, Tirthajyoti SARKAR, Min Kyung KO
  • Patent number: 10121890
    Abstract: An embodiment of a structure provides an enhanced performing high voltage device, configured as a lateral diffused MOS (HV LDMOS) formed in a tri-well structure (a small n-well in an extended p-type well inside an n-type well) within the substrate with an anti-punch through layer and a buried layer below the n-type well, which reduces substrate leakage current to almost zero. The drain region is separated into two regions, one within the small n-well and one contacting the outer n-type well such that the substrate is available for electric potential lines during when a high drain voltage is applied.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 10103223
    Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 10079177
    Abstract: A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with H2 gas at a first pressure. The cobalt layer is treated with a H2 plasma at a second pressure. The second pressure is lower than the first pressure.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 18, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Ko-Wei Lin, Ying-Lien Chen, Chun-Ling Lin, Huei-Ru Tsai, Hung-Miao Lin, Sheng-Yi Su, Tzu-Hao Liu
  • Publication number: 20180261537
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Application
    Filed: March 22, 2017
    Publication date: September 13, 2018
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Patent number: 10068836
    Abstract: An integrated circuit includes a substrate, a first inter-layer dielectric (ILD) layer over the substrate, and a gate strip having a first width formed in the first ILD layer. A conductive strip having a second width is provided on the gate strip, with the second width being greater than the first width. The conductive strip is positioned so that the gate strip is covered and a portion of the conductive strip extends over a top surface of the first ILD adjacent the gate strip. A second ILD layer is provided over the conductive strip and the first ILD layer with a contact plug extending through the second ILD layer to provide electrical contact to the conductive strip.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Ho, Chih-Ping Chao, Hua-Chou Tseng, Chun-Hung Chen, Chia-Yi Su, Alex Kalnitsky, Jye-Yen Cheng, Harry-Hak-Lay Chuang
  • Patent number: 10054749
    Abstract: An optical chip-scale package (CSP) is provided for use in a high channel density, high data rate communications system that has optical I/O ports and that is capable of being housed in a standard rackmount-sized box. The optical I/O ports comprise a bulkhead of multi-optical fiber (MF) adapters installed in a front panel of a switch box that houses the communications system. The adapters have first and second receptacles that are adapted to mate with first and second MF connectors, respectively. The communications system comprises a single-harness optical subassembly that uses a plurality of the optical CSPs that interface with a switch IC chip of the communications system to perform electrical-to-optical and optical-to-electrical conversion.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: August 21, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Tak Kui Wang, Chung-Yi Su, Nick Jordache
  • Publication number: 20180235001
    Abstract: Certain aspects of the present disclosure relate to methods and apparatus for implementing one or more ECCE index determinations for MPDCCH in special subframes in eMTC using communications systems operating according to new radio (NR) technologies. For example, a method for wireless communications may include determining a type of channel is scheduled to be transmitted across multiple subframes, determining a first subframe of the multiple subframes is of a first subframe type that is different than a second subframe type of one or more other subframes of the multiple subframes, and determining resources for a decoding candidate of a channel based, at least in part, on the first subframe type and the second subframe type.
    Type: Application
    Filed: September 22, 2017
    Publication date: August 16, 2018
    Inventors: Alberto RICO ALVARINO, Tom SESNIC, Yi SU, Wanshi CHEN
  • Patent number: 10018787
    Abstract: A wavelength division multiplexing and demultiplexing (WDM) assembly is provided that is also capable of performing bidirectional communications. The WDM assembly comprises a WDM module and an adapter for use with the WDM module. The adapter has first and second receptacles in front and back ends thereof, respectively, that are configured to mate with a multi-fiber (MF) connector and with the WDM module, respectively. The MF connector holds ends of M optical fibers and the WDM module has M lenses. The WDM module holds ends of N optical fibers, where N is equal to or greater than 2M. When the MF connector and the WDM module are mated with the first and second receptacles, respectively, the ends of the M optical fibers held in the MF connector are in optical alignment with M lenses, respectively, disposed in the WDM module.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 10, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Tak Kui Wang, Chung-Yi Su