Abstract: The disclosure provides a power semiconductor device and manufacturing method thereof. A plurality of second resistive field plate structures extending through an epitaxial layer in a first direction into a substrate are arranged in a termination region of the epitaxial layer and the plurality of second resistive field plate structures are arranged radially in a first plane. A plurality of tightly coupled second resistive field plates extending from a side close to a cell region to a side far away from the cell region form a more uniform three-dimensional electric field distribution diverging around the cell region, which optimizes a guiding and binding effect on a charge in a space depletion region of the cell region and improves a withstand voltage performance of the whole power semiconductor device.

Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.

Abstract: A trench gate semiconductor includes a substrate having a first conductivity type; an epitaxial layer having the first conductivity type, grown on the substrate; a well region having a second conductivity type, formed on a surface layer of the epitaxial layer; a source region having the first conductivity type, formed on a surface layer of the well region; a first trench, running through the well region from a surface of the source region to the epitaxial layer; a gate, formed in the first trench in a manner of being separated by a gate insulator; and an amorphous semiconductor layer, formed in the first trench and wrapping an outer bottom wall of the gate and corners on two sides of the outer bottom wall in a manner of being separated by the gate insulator, where the amorphous semiconductor layer is made of a low dielectric constant material.

Abstract: A communication method and an apparatus are provided. An example method includes: receiving initially transmitted first data in a first cell based on a correspondence between the first cell and a first hybrid automatic repeat request (HARQ) entity; receiving first indication information, wherein the first indication information indicates a correspondence between a second cell and the first HARQ entity; and receiving retransmitted first data in the second cell based on the correspondence between the second cell and the first HARQ entity.

Abstract: According to one aspect, an abrasive article includes a backing; a make coat overlying the backing; an abrasive layer comprising abrasive particles and a binder; wherein the abrasive particles comprise a random rotational orientation; wherein the abrasive particles comprise a total height, H, and a fracture feature located at a height of 55%-90% H. The fracture feature is configured to enable fracturing when the particle has a front facing orientation relative to the grinding direction relative to the amount of fracturing when the particle is in a side facing orientation relative to the grinding direction.

Abstract: A cleaning composition for electronics industries is provided. The cleaning composition includes 40% to 90% by weight of an amine solvent having a structure of following formula (1), a quaternary ammonium salt, and water. Wherein, R1, R2, R4, and R5 are each independently hydrogen, a linear alkyl group having 1 to 4 carbon atoms, a branched alkyl group having 3 to 5 carbon atoms, a linear alkylamine having 1 to 4 carbon atoms, or a branched alkylamine having 3 to 5 carbon atoms, and R3 is a linear alkylene group having 1 to 5 carbon atoms or a branched alkylene group having 3 to 5 carbon atoms.

Abstract: An interactive system is configured to be extensible, allowing use of plugins that detect content entry input of each of the one or more users on a user-generated content of a canvas. In response to detecting each content entry input, (i) the interactive system (i) automatically triggers execution of a plugin, the plugin being implemented as a program that executes separately from the interactive system; and (ii) renders at least a first output generated by execution of the plugin with the user-created content.

Abstract: A method for manufacturing the semiconductor structure includes following operations. A base is provided. A plurality of stack structures spaced apart from each other along a first direction are formed on a surface of the base and a plurality of first isolation layers arranged between the plurality of stack structures are formed, the plurality of stack structures include a plurality of first interlayer dielectric layers, a plurality of initial active layers and a plurality of second interlayer dielectric layers. Portion of each initial active layer is etched to form a first trench in each initial active layer. A plurality of oxide semiconductor layers are formed in a plurality of first trenches. Portions of the plurality of oxide semiconductor layers and remaining portions of the plurality of initial active layers are etched to form a plurality of active structures arranged in an array along the first direction and a second direction.

Abstract: Disclosed herein are second near-infrared (NIR-II) fluorescent composite and its production method. The method mainly includes the steps of, mixing a gold nanocluster having a plurality of a thiol-based compound on its outer surface and alpha-glycerylphosphorylcholine (alpha-GPC) in a solvent to form a mixture; replacing the solvent with an inert gas; and heating the mixture at a temperature about 100-200° C. in the presence of the inert gas until at least a portion of the gold nanocluster is encapsulated by a capping layer consisting of alpha-GPC, thereby producing the NIR-II fluorescent composite. The thus-produced NIR-II fluorescent composite is characterized by having an emission wavelength covering NIR-II region detectable by specialized camera. Also encompassed in the present disclosure is a method for conducting in vivo bioimaging of a target area in a subject.

Abstract: A method for fabricating a semiconductor structure and the device are disclosed. The method includes: providing a first sacrificial layer and semiconductor columns on a substrate; forming an isolation structure, disposed between adjacent stacked structures along the first direction; etching the isolation structure to form a through-hole, the through-hole exposes a part of the surface of the substrate, and also exposes each side of each stacked structure; along the second direction, the width of the bottom of the through-hole is greater than the width of the top of the through-hole, and the second direction is perpendicular to the first direction; the first sacrificial layer exposed by the through-hole is laterally etched, and a part of the first sacrificial layer is removed. A sacrificial layer exposes the top surface and the bottom surface of each semiconductor column. The present disclosure improves the morphology of the semiconductor structure.

Abstract: The semiconductor structure comprises: semiconductor channels, first gate structures, second gate structures and bit lines. Each semiconductor channel extends in a third direction and has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels comprises a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall comprises a first face extending in a first direction and a second face extending in a second direction. Each first gate structure is in contact with the first face. Each second gate structures is in contact with the second face, each first gate structure is in contact with the respective second gate structure. The bit lines extend in the second direction and are located on a side of each of the semiconductor channels in the third direction.

Abstract: A transistor includes a source structure, a trench, a drain structure, and a gate structure. The trench sequentially has first and second end faces which are arranged opposite in a first direction. The source structure extends from the first end face in a second direction. The source structure sequentially has third and fourth end faces which are arranged opposite in the first direction. The fourth end face is connected to the first end face. The drain structure extends from the second end face in a direction opposite to the second direction. The drain structure sequentially has fifth and sixth end faces which are arranged opposite in the first direction. The fifth end face is connected to the second end face. The second direction intersects the first direction. The gate structure surrounds the trench and is connected to the fourth and the fifth end face.

Abstract: A measurement method for a device includes, for each antenna group other than a target antenna group in an antenna array, determining compensation values of the antenna group based on characteristic parameters of the antenna group and characteristic parameters of the target antenna group, and adjusting, based on the compensation values of the antenna group, an electromagnetic wave transmitted by each antenna unit in the antenna group such that electromagnetic waves transmitted by all antenna units in the antenna array have a same phase or amplitude when the electromagnetic waves arrive at a measurement probe of a second device, where the electromagnetic wave is used to measure an over-the-air beam parameter of the first device, and a distance between the first device and the measurement probe is less than a far-field boundary distance.

Abstract: Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate; forming, on a surface of the substrate, stacked structures arranged at intervals in a first direction and a first isolation layer located between adjacent stacked structures, the stacked structure including a first interlayer dielectric layer, an initial active layer, and a second interlayer dielectric layer; etching a portion of the initial active layer to form a first trench; forming a metal conductive layer in the first trench, the metal conductive layer being in contact connection with the remained initial active layer; and etching a portion of the metal conductive layer to form lower electrode structures arranged in an array in the first direction and a second direction, where the first direction is perpendicular to the surface of the substrate, and the second direction is parallel to the surface of the substrate.

Abstract: The present disclosure provides a human machine interface panel including a main body and a fixing device. The main body includes a housing and a first contact surface. The fixing device includes a base, a self-tapping screw and a bottom base. The base is detachably connected to the housing and has a mounting hole. The self-tapping screw penetrates through the mounting hole and has an interference fit to the mounting hole. The bottom base is disposed at an end of the self-tapping screw. By disposing a plate between the bottom base and the first contact surface, and tightening the self-tapping screw, the plate is clamped by the bottom base and the first contact surface. Consequently, the human machine interface panel is fixed to the plate.

Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an active pillar including a channel region and a source/drain region arranged on two sides of the channel region; and a gate structure surrounding at least part of the channel region. The channel region includes a peripheral portion and a central portion, the peripheral portion is positioned between the gate structure and the central portion, the source/drain region and the peripheral portion have a first doping type, and the central portion has a second doping type, where the first doping type is one of N-type and P-type, and the second doping type is other one of the N-type and the P-type. At least problems of greater difficulty in turning off existing junctionless field effect transistor and poorer turn-off effect may be solved.

Abstract: A method for forming a semiconductor structure includes the following operations. A substrate is provided and includes a stacked structure and a first isolation structure that are alternately arranged in a first direction. A grid-like etched groove extending in the first direction is formed in the stacked structure and the first isolation structure, and divides the substrate into a first region and a second region that are arranged sequentially in a second direction. The first direction and the second direction are any two directions in a plane where the substrate is located. A second isolation structure is formed in the grid-like etched groove. A transistor structure and a capacitor structure are respectively formed in the first region and the second region, and are isolated by the second isolation structure.

Abstract: Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a source doped region, a drain doped region, and a lightly doped region and an intrinsic region that are arranged adjacent to each other and located between the source doped region and the drain doped region. The lightly doped region is adjacent to the source doped region, and the intrinsic region is adjacent to the drain doped region. A doping concentration of the source doped region and the drain doped region is greater than a doping concentration of the lightly doped region.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: an active pillar, where the active pillar includes: a channel region, as well as a first doped region and a second doped region located at two sides of the channel region, the channel region, the first doped region, and the second doped region having a same doping type, where a counter-doped region is arranged in the channel region, the counter-doped region is close to the first doped region, and a doping type of the counter-doped region is different from a doping type of the channel region; and a gate, where the gate surrounds a part of the channel region, and in a plane in which an axis of the active pillar is located, projection of the gate partially overlaps with projection of the counter-doped region.