Abstract: One-part condensation curable silyl-modified polymer (SMP) based sealant compositions in particular one-part condensation curable SMP based sealant compositions containing a catalyst comprising (i) a titanate and/or zirconate and (ii) a metal carboxylate salt which compositions upon cure provide elastomeric sealants having low modulus and a high elastic recovery.

Abstract: An electronic package is provided, in which a carrier structure provided with electronic components is disposed onto an antenna structure, where a stepped portion is formed at an edge of the antenna structure, so that a shielding body is arranged along a surface of the stepped portion. Therefore, the shielding body only covers a part of the surface of the antenna structure to prevent the shielding body from interfering with operation of the antenna structure.

Abstract: A method for programming the energy storage device in power-gas coupling system based on reliability constraints is provided. The method includes: obtain the parameters and operation condition of each equipment of the power-gas coupling system in a year; determine the different operating states of the system. A programming model of the energy storage device based on reliability constraints is constructed based on the operating state of the system, and benders decomposition algorithm is adopted to calculate the programming model, so that the programming scheme of the energy storage device is obtained. Considering not only the economy but also the reliability of the system, which is more accurate, comprehensive and effective than the previous programming method; the present invention is of great significance to improve the reliability of the electric power system and ensure the safe and reliable operation of the electric power system.

Abstract: A method for forming a semiconductor structure comprises: providing a substrate, which includes a first area and a second area arranged in sequence in a second direction, the first area including active layers arranged at intervals in a third direction; forming an initial gate structure located on a surface of each active layer in the first area; etching the initial gate structures to form comb-shaped gate structures stacked in a third direction, each comb-shaped gate structure including first gate structures arranged at intervals in the first direction; and forming bit line structures extending in the third direction and capacitor structures extending in the second direction in the second area, the bit line structures and the capacitor structures are connecting to the first gate structures.

Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.

Abstract: Embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The method includes: providing a semiconductor substrate including a plurality of active pillars arranged at intervals; etching the active pillar to form an annular groove, in which the annular groove does not expose a top surface and a bottom surface of the active pillar; and forming a first semiconductor layer in the annular groove to form the semiconductor structure; in which a band gap of the first semiconductor layer is smaller than a band gap of the active pillar.

Abstract: Embodiments provide a semiconductor structure and a method thereof. The method includes: providing a first substrate, and forming a drive pad on the first substrate; providing a second substrate, and forming active pillars and a bit line in sequence on a side of the second substrate, wherein a side of the bit line is connected to the active pillars, and a surface of the bit line facing away from the active pillars is exposed on a surface of the second substrate; bonding the bit line to the drive pad correspondingly; thinning the second substrate from a side of the second substrate facing away from the first substrate until the active pillars are exposed; and forming a storage capacitor on sides of the active pillars facing away from the drive pad, the storage capacitor being connected to the active pillars.

Abstract: Embodiments of the disclosure provide a semiconductor substrate, a method for forming same, and a layout structure. The method includes: providing a semiconductor structure including a first region and a second region arranged in sequence along a second direction, the second region including active structures arranged in an array along a first direction and a third direction, each of the active structure at least including a channel structure, the first direction, the second direction, and the third direction being perpendicular to each other, and the first direction and the second direction being parallel to a surface of the semiconductor substrate; forming a gate structure on a surface of the channel structure; and forming a word line structure extending in the first direction on the first region. The word line structure is connected with the gate structure located on the same layer.

Abstract: Embodiments relate to a semiconductor device and a forming method. The semiconductor device includes: a substrate; a memory array positioned on the substrate and at least including memory cells spaced along a first direction, each of the memory cells including a transistor, the transistor including a gate electrode, channel regions distributed on two opposite sides of the gate electrode along a third direction, and a source region and a drain region distributed on two opposite sides of each of the channel regions along a second direction, the first direction and the third direction being directions parallel to a top surface of the substrate, the first direction intersecting with the third direction, and the second direction being a direction perpendicular to the top surface of the substrate; and a word line extending along the first direction and continuously electrically connected to the gate electrodes spaced along the first direction.

Abstract: A method for forming a semiconductor structure includes the following: a substrate is provided, the substrate including a first area and a second area arranged in sequence in a second direction and T-shaped active pillars located in the first area and the second area and arranged in an array in a first direction and a third direction, the first, second and third directions being perpendicular to one another, and the first and second directions being parallel to a surface of the substrate; T-shaped gate structures located on surfaces of the T-shaped active pillars and bit line structures extending in the third direction are formed in the first area, a plurality of T-shaped gate structures located in the first direction being interconnected; and capacitor structures extending in the second direction is formed in the second area, the bit line structures and the capacitor structures being connected to the T-shaped gate structures.

Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor structure, including a substrate and connection lines. Structural cells arranged in an array are provided on the substrate, and include transistor groups arranged in a first direction, and the transistor groups include multi-layer transistors extending in a second direction. The first direction is perpendicular to the second direction, and both are parallel to a surface of the substrate. The structural cells further include bit lines extending in a third direction, the bit lines are electrically connected to the multi-layer transistors in the same transistor group, where the third direction is perpendicular to the surface of the substrate. The connection lines are connected to the bit lines in the structural cells in one-to-one correspondence, and one bit line in the structural cells arranged in the array is connected to the same connection line.

Abstract: The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, at least a gate structure, a first dielectric layer covering a surface of the substrate and the gate structure being formed on the substrate, and a first dielectric layer on a side surface of the gate structure serving as a first sidewall; forming a sacrificial sidewall on a side surface of the first sidewall; removing the sacrificial sidewall after a first doped region and a second doped region are respectively formed in the substrate on both sides of the sacrificial sidewall; forming a second sidewall on a side surface of the first sidewall.

Abstract: Provide is a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method includes the following operations. A substrate is provided. Multiple silicon pillars are formed in the substrate, and extend along a first direction. In the first direction, each of the silicon pillars includes a first portion and a second portion. An insulating layer is formed in the second portion of the silicon pillar. A conductive layer is formed in the first portion of the silicon pillar. A capacitor layer is formed on surfaces of the insulating layer and the conductive layer of the silicon pillar.

Abstract: A method for evaluating drilling fluid includes making an NMR measurement of a sample of the drilling fluid and inverting the measurements to compute a corresponding T1T2 plot. The T1T2 plot is in turn evaluated to characterize the drilling fluid. In one embodiment, a stability index of the fluid may be computed from multiple NMR measurements made while aging the sample.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

Abstract: An ultrasonic transducer includes a carrier with a first surface and a second surface which are opposite to each other, a piezoceramic element attached on the first surface of the carrier, a first acoustic matching layer with a third surface and a fourth surface which are opposite to each other, the third surface is attached on the second surface of the carrier, wherein the first acoustic matching layer includes a mesh with openings, and the thickness of first acoustic matching layer is smaller than ¼ wavelength of an ultrasonic wave emitted by the piezoceramic element in the first acoustic matching layer in an operating frequency, and a total area of the openings of mesh is larger than 30% area of the third surface of first acoustic matching layer, and a second acoustic matching layer disposed on the fourth surface of the first acoustic matching layer.

Abstract: The invention discloses a method for correcting the pointing errors of a biaxial rotation system based on the spherical cap function, comprising: error collection: selecting stars or radio sources distributed evenly in a star catalogue for tracking and observation to obtain the theoretical position and measurement position of the stars, and subtracting the measurement positions and the theoretical positions to obtain the error distribution; error model fitting: selecting a suitable orthogonal spherical cap function for the obtained error distribution and performing fitting to calculate an error fitting coefficient, the orthogonal spherical cap function model comprising a hemispheric harmonic function HSH, a Zernike spherical cap function ZSF, and a longitudinal spherical cap function LSF; and error control and compensation: putting the error model and the related fitting coefficient into a pointing control system for compensation.

Abstract: A hardware-based fan controller for controlling fan modules in a computer system having multiple computer nodes is disclosed. Each of the computer nodes has a service processor. The fan controller includes a slave module that receives fan speed commands from each of the service processors. A fan speed generator is coupled to the slave module and a subset of the fan modules. The fan speed generator receives fan speed commands from the slave module and fan speed outputs from the subset of fan modules. The fan speed generator is configured to output a speed command to each of the fan modules in the subset.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.