Abstract: CLLC resonant converters using full-bridge (FB) and half-bridge (HB) soft-morphing techniques are disclosed. Two forms of soft-morphing are provided: type1, steady-state rotational soft-morphing, which ensures balanced power loss and thermal stress across all power switches, and type2, dynamic soft-morphing, which facilitates smooth transitions between FB-FB, FB-HB, and HB-FB modes. Consequently, the FB CLLC resonant converter can achieve a 16× ultra-wide voltage gain range.

Abstract: In an aspect of the disclosure, an operation method, for balancing voltage of capacitors of a bridge circuit of a multi-level LLC resonant converter, includes: measuring voltages of the capacitors of the bridge circuit, an output voltage and an output current of an output load the multi-level LLC resonant converter, and an input voltage of the bridge circuit; selecting a voltage-level zone of a required output voltage of the bridge circuit according to the output voltage of the output load, and the input voltage of the bridge circuit; selecting a circuit mode, with a highest value of the required output voltage; and outputting PWM signals corresponding to the circuit mode, with a switching frequency, to switches of the plurality of capacitor-switch modules.

Abstract: A zero-voltage soft switching (ZVS soft switching) control method and a power control circuit using the same are provided. The ZVS shot switching control method includes the following steps. A trapezoidal current control is executed to shape an inductor current into a plurality of trapezoidal waveforms.

Abstract: Devices and methods are provided for adaptively optimizing load sharing to minimize power consumption. A controller receives an initial input power supplied by multiple power stages of a power supply unit to an electronic device. The controller adaptively configures load sharing settings of one or more power stages based on the initial input power and one or more parameters associated with the electronic device to achieve a minimum input power consumption. The power stage(s) exhibits uneven load sharing based on the load sharing settings. To supply an updated input power to the electronic device, the controller controls the power stage(s) based on the load sharing settings. The initial input power and the updated input power correspond to a total power consumption of the electronic device. The controller performs continuous monitoring, real-time analysis, and adaptive adjustments to optimize power usage based on specific hardware characteristics, environmental conditions, and dynamic load behavior.

Abstract: A distributed generation unit (DGU) is provided. The DGU includes a meter and a processor. The meter generates a per-unit current based on the rated power value of the DGU. The processor is coupled between a control area network (CAN) bus and the circuit block. The processor causes the DGU to identify a first electrical signal at an initial time and perform a master selection process. The master selection process includes determining the delay time based on the per-unit current and the maximum per-unit current, identifying the per-unit current as the maximum per-unit current when the delay time has elapsed since the initial time, and broadcasting the maximum per-unit current and a second electrical signal through the CAN bus. The processor is further configured to perform a droop coefficient regulation process to maintain the current state of the DGU after the second electrical signal is broadcast.

Abstract: Existing power consumption management strategies respond to power usage spikes only after they occur, increasing the risk of circuit breaker trips and unexpected shutdowns. To address this, devices, systems, methods, and processes for facilitating dynamic power regulation are described herein. A network device in a network monitors one or more power usage metrics associated with the network device and compares the power usage metrics with a threshold value. Based on determining that the power usage metrics are greater or equal to the threshold value, the network device detects a power surge event. The network device mimics, based on the detection of the power surge event, a congestion event causing a reduction in an initial data throughput of the network device to a diminished data throughput that decreases power consumption in the network device. Thus, making the network device to recover from the power surge event.

Abstract: The semiconductor structure comprises: semiconductor channels, first gate structures, second gate structures and bit lines. Each semiconductor channel extends in a third direction and has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels comprises a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall comprises a first face extending in a first direction and a second face extending in a second direction. Each first gate structure is in contact with the first face. Each second gate structures is in contact with the second face, each first gate structure is in contact with the respective second gate structure. The bit lines extend in the second direction and are located on a side of each of the semiconductor channels in the third direction.

Abstract: Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate; forming, on a surface of the substrate, stacked structures arranged at intervals in a first direction and a first isolation layer located between adjacent stacked structures, the stacked structure including a first interlayer dielectric layer, an initial active layer, and a second interlayer dielectric layer; etching a portion of the initial active layer to form a first trench; forming a metal conductive layer in the first trench, the metal conductive layer being in contact connection with the remained initial active layer; and etching a portion of the metal conductive layer to form lower electrode structures arranged in an array in the first direction and a second direction, where the first direction is perpendicular to the surface of the substrate, and the second direction is parallel to the surface of the substrate.

Abstract: The method includes: providing an initial structure including a plurality of dielectric layers and a plurality of conductive layers, where each of the plurality of conductive layers includes a plurality of conductive strips, a plurality of first holes penetrate through the plurality of conductive strips along a first direction; laterally thinning the plurality of conductive strips to form a plurality of first trenches; forming a plurality of first indium gallium zinc oxides in the plurality of first trenches; laterally thinning the plurality of dielectric layers to expose part of the plurality of first indium gallium zinc oxides; forming a plurality of second indium gallium zinc oxides on the surfaces of the plurality of exposed first indium gallium zinc oxides, where the concentration of indium in the plurality of first indium gallium zinc oxides is higher than that of indium in the plurality of second indium gallium zinc oxides.

Abstract: A method includes receiving, a record containing clinical information associated with a patient; applying the record a set of machine-learned models including: a medical entity extraction model that is configured to extract medical entities from the clinical information; a medical ontology mapping model that is configured to associate one or more candidate medical codes with each of the medical entities based on vector embedding similarities and to rank each of the one or more candidate medical codes based on their similarities, respectively, with the associated medical entity; and a validation model that is configured to categorize an association between one or more pairs of the one or more candidate medical codes into one or more confidence ratings, respectively; generating a suggested medical code for each of the medical entities based on the rank of the one or more candidate medical codes associated therewith and the one or more confidence ratings of the one or more candidate medical codes, respectively;

Abstract: The present disclosure provides compositions and methods for treating a disease or condition in a subject in need thereof, comprising administering to the subject a pharmaceutically effective amount of a composition comprising a plurality of particles comprising at least one therapeutic biologic suspended in a pharmaceutically acceptable liquid carrier.

Abstract: A method for forming a semiconductor structure includes the following: a substrate is provided, the substrate including a first area and a second area arranged in sequence in a second direction and T-shaped active pillars located in the first area and the second area and arranged in an array in a first direction and a third direction, the first, second and third directions being perpendicular to one another, and the first and second directions being parallel to a surface of the substrate; T-shaped gate structures located on surfaces of the T-shaped active pillars and bit line structures extending in the third direction are formed in the first area, a plurality of T-shaped gate structures located in the first direction being interconnected; and capacitor structures extending in the second direction is formed in the second area, the bit line structures and the capacitor structures being connected to the T-shaped gate structures.

Abstract: Technologies for compilers that implement non-power of two Fast Fourier Transform (FFT) algorithms are described. The non-power of two FFT algorithm uses a recursive function to generate a hardware design of a set of compute blocks of a fixed-point digital signal processor (DSP) and routing data between the compute blocks. The compiler receives input specifying a sequence of indexes and a bit width of the fixed-point DSP and performs a process. The process splits the sequence using a recursive loop, determines a number of multiplications in the hardware design, and generates a trace graph of the non-power of two FFT algorithm. The process is entered via the recursive function and exists when the recursive loop decrements to a specified value corresponding to a Radix-3 or Radix-2. The compiler outputs data, including the hardware design, the number of multiplications in the hardware design, and the trace graph.

Abstract: A transistor includes a source structure, a trench, a drain structure, and a gate structure. The trench sequentially has first and second end faces which are arranged opposite in a first direction. The source structure extends from the first end face in a second direction. The source structure sequentially has third and fourth end faces which are arranged opposite in the first direction. The fourth end face is connected to the first end face. The drain structure extends from the second end face in a direction opposite to the second direction. The drain structure sequentially has fifth and sixth end faces which are arranged opposite in the first direction. The fifth end face is connected to the second end face. The second direction intersects the first direction. The gate structure surrounds the trench and is connected to the fourth and the fifth end face.

Abstract: Technologies directed to carrier frequency offset (CFO) compensation is described. An input buffer receives a first set of incoming samples associated with a first frequency from an incoming data stream. A first outgoing sample of an outgoing data stream is generated using the first set of incoming samples. The first outgoing sample is associated with a second frequency. A ratio between the first and second frequencies is used to determine that the first outgoing sample is associated with a misalignment between the incoming data stream and the outgoing data stream. The input buffer receives a second set of incoming samples associated with the first frequency from the incoming data stream. A second outgoing sample of the outgoing data stream is generated using the second set of incoming samples. The second outgoing sample is associated with the second frequency. The first outgoing sample is overwritten by the second outgoing sample.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base and a bit line that extends along a first direction; active structures, wherein the active structure includes at least two active layers arranged at intervals, the active layer includes a first source-drain region, a channel region, a second source-drain region, and a support region, and the bit line is connected to the first source-drain region; a word line extending along a second direction, wherein the word line is connected to an adjacent active structure, and the word line surrounds at least two channel regions included in the connected active structure; and a memory structure perpendicularly stacked on the base, where the memory structure is connected to the second source-drain region, and the memory structure surrounds the support region.

Abstract: A semiconductor structure and a fabrication method therefor are provided. The fabrication method includes: A substrate and a stacked structure formed on the substrate are provided; vias running through the stacked structure in the vertical direction are formed; a sidewall protective layer is formed on an inner wall of each of the vias; a bottom protective layer is formed on the partial surface of the substrate exposed by each of the vias; each of the vias is filled with an isolation layer; the isolation layer s and a part of the sidewall protective layer in each of the first hole are removed, and a transistor structure is formed in each of the first holes; and the isolation layer and a part of the sidewall protective layer in each of the second holes are removed, and a capacitor structure is formed in each of the second holes.

Abstract: Provided are a ferroelectric memory, a three-dimensional ferroelectric memory, and a three-dimensional ferroelectric memory device. The ferroelectric memory includes a first word line, a first bit line, a first transistor, and a first ferroelectric capacitor pair. The first ferroelectric capacitor pair includes a first ferroelectric capacitor and a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor extend in a first direction. A control terminal of the first transistor is connected to the first word line. A second terminal of the first transistor is connected to the first bit line, and a first terminal of the first transistor is connected to upper electrode plates of the ferroelectric capacitor pair.

Abstract: The present invention provides a reactive fluorosurfactant, and a preparation method therefor and a use thereof. The reactive fluorosurfactant is a polymer of which a main chain contains the following structural units: (A), (B), and (C). The reactive fluorosurfactant provided in the present invention has a good effect of reducing the surface tension of an aqueous phase system, and can be used in an aqueous emulsion polymerization method to prepare a fluoropolymer; moreover, the reactive fluorosurfactant participates in a polymerization reaction, and a fluoropolymer emulsion prepared by using the reactive fluorosurfactant is stable and has no phenomenon of emulsion breaking.

Abstract: A polytetrafluoroethylene dispersion resin for a dry electrode binder and a preparation method thereof. The polytetrafluoroethylene dispersion resin prepared by the method does not contain PFOA, the SSG is 2.150 to 2.160, the average particle size is 10 to 100 ?m, has excellent fiber forming performance and a high fiber forming rate, and is not prone to wire breakage. When the electrode binder is used as a dry electrode binder, active carbon particles and conductive agent particles can be contacted more tightly in a fiber state, such that the electrode has the advantages of large density, excellent conductivity, high capacity, etc.