Abstract: In an aspect of the disclosure, a pulse generator for applying to a multilevel DC-DC converter including a filter is provided. The pulse generator includes a controller and multiple capacitor-switch modules coupled to the controller and configured to receive an input voltage of the multilevel DC-DC converter and output an inductor current with a trapezoidal waveform on an inductor of the filter.

Abstract: The present invention discloses a spatial parallelogram connecting rod structure and a miniaturized mechanical arm having same and application, comprising a rotating base, a triaxial mechanical arm and a spatial parallelogram connecting rod structure. An installation housing is fixed on a rotating base, and a fixed part of the rotating base is installed on a supporting apparatus of a medical device; the rotating output end of the second rotating body is provided with a turntable forearm, and an edge of the turntable forearm is hinged with a forearm oscillating bar; an output control body is provided with two hinged points which are hinged with the ends of the large arm oscillating bar and the forearm oscillating bar respectively; and the output control body is fixed on a shell of a first rotating part of the triaxial mechanical arm.

Abstract: A method for configuring reactive power capacity of a power grid to which offshore wind power is connected on a large scale includes the following steps. Static voltage stability index of substations in a regional power grid to which the offshore wind power is connected on the large scale and at multiple points and relative dynamic voltage drop area index for an N-2 fault are calculated. Thus, weak nodes in voltage stability are located, thereby implementing a prediction of a risk to the voltage stability of the regional power grid. These nodes are used as candidate reactive power compensation configuration nodes. An objective function is established as the minimum total cost of reactive power compensation devices at the candidate reactive power compensation configuration nodes. A multi-type reactive power optimization configuration model including static voltage stability constraints, voltage stability constraints under faulty state, and other constraints is solved.

Abstract: Optical modules are provided. In one aspect, an optical module includes a printed circuit board (PCB) and a cover having a flange coupled with the PCB. The PCB and the cover are sealed such that when the PCB and the cover are disposed in an immersion fluid the PCB and the cover collectively define a sealed interior that is fluidly isolated from the immersion fluid. The optical module also includes an optical fiber and an electro-optical package disposed in the sealed interior. The electro-optical package has a lens body providing an optical path along which optical signals travel. The optical fiber is in free space optical communication with the optical path of the lens body. A fiber escape is formed by the flange and the PCB, allowing the optical fiber to escape the sealed interior into the immersion fluid.

Abstract: The present disclosure provides compositions and methods for treating a disease or condition in a subject in need thereof, comprising administering to the subject a pharmaceutically effective amount of a composition comprising a plurality of particles comprising at least one therapeutic biologic suspended in a pharmaceutically acceptable liquid carrier.

Abstract: Provided are a special fiber bundle, an optical receiving system based on the special fiber bundle, and a lidar based on the optical receiving system, relating to the technical field of airborne bathymetric lidar. The special fiber bundle includes an input end, a first output end, and a second output end. The input end is composed of a central multimode fiber, and an annular multimode fiber bundle surrounding the central fiber; the first output end is a central multimode fiber; and the second output end is a circular fiber bundle formed by the annular multimode fiber bundle of the input end.

Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an active pillar including a channel region and a source/drain region arranged on two sides of the channel region; and a gate structure surrounding at least part of the channel region. The channel region includes a peripheral portion and a central portion, the peripheral portion is positioned between the gate structure and the central portion, the source/drain region and the peripheral portion have a first doping type, and the central portion has a second doping type, where the first doping type is one of N-type and P-type, and the second doping type is other one of the N-type and the P-type. At least problems of greater difficulty in turning off existing junctionless field effect transistor and poorer turn-off effect may be solved.

Abstract: A method for forming a semiconductor structure includes the following operations. A substrate is provided and includes a stacked structure and a first isolation structure that are alternately arranged in a first direction. A grid-like etched groove extending in the first direction is formed in the stacked structure and the first isolation structure, and divides the substrate into a first region and a second region that are arranged sequentially in a second direction. The first direction and the second direction are any two directions in a plane where the substrate is located. A second isolation structure is formed in the grid-like etched groove. A transistor structure and a capacitor structure are respectively formed in the first region and the second region, and are isolated by the second isolation structure.

Abstract: Disclosed is a reactive power control method for suppressing a transient overvoltage in a DC sending-end power grid of new energy. The method estimates the trend of grid voltage changes by using current and historical signals of the grid voltage, calculates the reactive power command offset value to achieve the effect of reactive power lead control, and combines the optimized reactive power value after lag compensation. The superposition of the lag compensation and the reactive power optimization generates a final command value for a new energy power source, and this command value can ensure that new energy effectively outputs reactive power to participate in the suppression of the transient overvoltage in a DC converter station.

Abstract: A method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory are provided. The method includes: a substrate is provided; a stack structure is formed on the substrate; the stack structure is divided into multiple channel areas, first source-drain areas and second source-drain areas. Each channel area extends in a second direction, each first source-drain area and each second source-drain area extend in a first direction, and the first source-drain area and the second source-drain area are located on the same side of the channel area; a first source-drain structure extending in the first direction is formed in the first source-drain area and a second source-drain structure extending in the first direction is formed in the second source-drain area; and a channel structure extending in the second direction is formed in the channel area.

Abstract: Embodiments provide a semiconductor structure and a method thereof. The method includes: providing a first substrate, and forming a drive pad on the first substrate; providing a second substrate, and forming active pillars and a bit line in sequence on a side of the second substrate, wherein a side of the bit line is connected to the active pillars, and a surface of the bit line facing away from the active pillars is exposed on a surface of the second substrate; bonding the bit line to the drive pad correspondingly; thinning the second substrate from a side of the second substrate facing away from the first substrate until the active pillars are exposed; and forming a storage capacitor on sides of the active pillars facing away from the drive pad, the storage capacitor being connected to the active pillars.

Abstract: CLLC resonant converters using full-bridge (FB) and half-bridge (HB) soft-morphing techniques are disclosed. Two forms of soft-morphing are provided: type1, steady-state rotational soft-morphing, which ensures balanced power loss and thermal stress across all power switches, and type2, dynamic soft-morphing, which facilitates smooth transitions between FB-FB, FB-HB, and HB-FB modes. Consequently, the FB CLLC resonant converter can achieve a 16× ultra-wide voltage gain range.

Abstract: In an aspect of the disclosure, an operation method, for balancing voltage of capacitors of a bridge circuit of a multi-level LLC resonant converter, includes: measuring voltages of the capacitors of the bridge circuit, an output voltage and an output current of an output load the multi-level LLC resonant converter, and an input voltage of the bridge circuit; selecting a voltage-level zone of a required output voltage of the bridge circuit according to the output voltage of the output load, and the input voltage of the bridge circuit; selecting a circuit mode, with a highest value of the required output voltage; and outputting PWM signals corresponding to the circuit mode, with a switching frequency, to switches of the plurality of capacitor-switch modules.

Abstract: A zero-voltage soft switching (ZVS soft switching) control method and a power control circuit using the same are provided. The ZVS shot switching control method includes the following steps. A trapezoidal current control is executed to shape an inductor current into a plurality of trapezoidal waveforms.

Abstract: Devices and methods are provided for adaptively optimizing load sharing to minimize power consumption. A controller receives an initial input power supplied by multiple power stages of a power supply unit to an electronic device. The controller adaptively configures load sharing settings of one or more power stages based on the initial input power and one or more parameters associated with the electronic device to achieve a minimum input power consumption. The power stage(s) exhibits uneven load sharing based on the load sharing settings. To supply an updated input power to the electronic device, the controller controls the power stage(s) based on the load sharing settings. The initial input power and the updated input power correspond to a total power consumption of the electronic device. The controller performs continuous monitoring, real-time analysis, and adaptive adjustments to optimize power usage based on specific hardware characteristics, environmental conditions, and dynamic load behavior.

Abstract: A distributed generation unit (DGU) is provided. The DGU includes a meter and a processor. The meter generates a per-unit current based on the rated power value of the DGU. The processor is coupled between a control area network (CAN) bus and the circuit block. The processor causes the DGU to identify a first electrical signal at an initial time and perform a master selection process. The master selection process includes determining the delay time based on the per-unit current and the maximum per-unit current, identifying the per-unit current as the maximum per-unit current when the delay time has elapsed since the initial time, and broadcasting the maximum per-unit current and a second electrical signal through the CAN bus. The processor is further configured to perform a droop coefficient regulation process to maintain the current state of the DGU after the second electrical signal is broadcast.

Abstract: Existing power consumption management strategies respond to power usage spikes only after they occur, increasing the risk of circuit breaker trips and unexpected shutdowns. To address this, devices, systems, methods, and processes for facilitating dynamic power regulation are described herein. A network device in a network monitors one or more power usage metrics associated with the network device and compares the power usage metrics with a threshold value. Based on determining that the power usage metrics are greater or equal to the threshold value, the network device detects a power surge event. The network device mimics, based on the detection of the power surge event, a congestion event causing a reduction in an initial data throughput of the network device to a diminished data throughput that decreases power consumption in the network device. Thus, making the network device to recover from the power surge event.

Abstract: The semiconductor structure comprises: semiconductor channels, first gate structures, second gate structures and bit lines. Each semiconductor channel extends in a third direction and has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels comprises a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall comprises a first face extending in a first direction and a second face extending in a second direction. Each first gate structure is in contact with the first face. Each second gate structures is in contact with the second face, each first gate structure is in contact with the respective second gate structure. The bit lines extend in the second direction and are located on a side of each of the semiconductor channels in the third direction.

Abstract: Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate; forming, on a surface of the substrate, stacked structures arranged at intervals in a first direction and a first isolation layer located between adjacent stacked structures, the stacked structure including a first interlayer dielectric layer, an initial active layer, and a second interlayer dielectric layer; etching a portion of the initial active layer to form a first trench; forming a metal conductive layer in the first trench, the metal conductive layer being in contact connection with the remained initial active layer; and etching a portion of the metal conductive layer to form lower electrode structures arranged in an array in the first direction and a second direction, where the first direction is perpendicular to the surface of the substrate, and the second direction is parallel to the surface of the substrate.

Abstract: The method includes: providing an initial structure including a plurality of dielectric layers and a plurality of conductive layers, where each of the plurality of conductive layers includes a plurality of conductive strips, a plurality of first holes penetrate through the plurality of conductive strips along a first direction; laterally thinning the plurality of conductive strips to form a plurality of first trenches; forming a plurality of first indium gallium zinc oxides in the plurality of first trenches; laterally thinning the plurality of dielectric layers to expose part of the plurality of first indium gallium zinc oxides; forming a plurality of second indium gallium zinc oxides on the surfaces of the plurality of exposed first indium gallium zinc oxides, where the concentration of indium in the plurality of first indium gallium zinc oxides is higher than that of indium in the plurality of second indium gallium zinc oxides.