Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an active pillar including a channel region and a source/drain region arranged on two sides of the channel region; and a gate structure surrounding at least part of the channel region. The channel region includes a peripheral portion and a central portion, the peripheral portion is positioned between the gate structure and the central portion, the source/drain region and the peripheral portion have a first doping type, and the central portion has a second doping type, where the first doping type is one of N-type and P-type, and the second doping type is other one of the N-type and the P-type. At least problems of greater difficulty in turning off existing junctionless field effect transistor and poorer turn-off effect may be solved.

Abstract: A method for forming a semiconductor structure includes the following operations. A substrate is provided and includes a stacked structure and a first isolation structure that are alternately arranged in a first direction. A grid-like etched groove extending in the first direction is formed in the stacked structure and the first isolation structure, and divides the substrate into a first region and a second region that are arranged sequentially in a second direction. The first direction and the second direction are any two directions in a plane where the substrate is located. A second isolation structure is formed in the grid-like etched groove. A transistor structure and a capacitor structure are respectively formed in the first region and the second region, and are isolated by the second isolation structure.

Abstract: Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a source doped region, a drain doped region, and a lightly doped region and an intrinsic region that are arranged adjacent to each other and located between the source doped region and the drain doped region. The lightly doped region is adjacent to the source doped region, and the intrinsic region is adjacent to the drain doped region. A doping concentration of the source doped region and the drain doped region is greater than a doping concentration of the lightly doped region.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: an active pillar, where the active pillar includes: a channel region, as well as a first doped region and a second doped region located at two sides of the channel region, the channel region, the first doped region, and the second doped region having a same doping type, where a counter-doped region is arranged in the channel region, the counter-doped region is close to the first doped region, and a doping type of the counter-doped region is different from a doping type of the channel region; and a gate, where the gate surrounds a part of the channel region, and in a plane in which an axis of the active pillar is located, projection of the gate partially overlaps with projection of the counter-doped region.

Abstract: A computing system operates to associate a layout logic with a plurality of object that are rendered on a canvas of a user device, where the plurality of objects include a parent object and multiple child objects contained within the parent object. The multiple child objects can be arranged to have a first collective span in a first axial direction and a second collective span in a second axial direction. In response to a first input, the computer system automatically implements the layout logic by (i) changing a dimension of the parent object in each of the first axial direction and second axial direction, and (ii) rearranging the multiple child objects within the parent object to change the first collective span and the second collective span.

Abstract: The present disclosure relates to a memory and a forming method thereof. The method of forming a memory includes: forming a stacked layer on a surface of a substrate, the stacked layer including interlayer isolation layers arranged at intervals in a first direction and a sacrificial layer group located between adjacent two of the interlayer isolation layers, the sacrificial layer group including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer sequentially stacked in the first direction, and the stacked layer including a transistor region, where the first direction is a direction perpendicular to a top surface of the substrate; removing the second sacrificial layer in the transistor region to form a first gap; and forming a gate layer and a channel layer wrapping the gate layer in the first gap.

Abstract: A method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory are provided. The method includes: a substrate is provided; a stack structure is formed on the substrate; the stack structure is divided into multiple channel areas, first source-drain areas and second source-drain areas. Each channel area extends in a second direction, each first source-drain area and each second source-drain area extend in a first direction, and the first source-drain area and the second source-drain area are located on the same side of the channel area; a first source-drain structure extending in the first direction is formed in the first source-drain area and a second source-drain structure extending in the first direction is formed in the second source-drain area; and a channel structure extending in the second direction is formed in the channel area.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a method of manufacturing a semiconductor structure and a semiconductor structure. The semiconductor structure includes a transistor region and a step region, the transistor region includes a word line region, the word line region directly faces and is connected to the step region, and the manufacturing method includes: providing a base and forming sacrificial layers and active layers on the base; forming first isolation layers in the transistor region, wherein the first isolation layers divide a part of the active layers into a plurality of active structures; removing a part of the first isolation layers and a part of the sacrificial layers in the word line region; forming word lines and dielectric layers in the word line region, wherein the step region includes a first region and second regions located on two sides of the first region.

Abstract: The present disclosure relates to a semiconductor structure, including a columnar epitaxial structure, a grounding structure, a bit line structure, a columnar capacitor structure, and a word line structure. The columnar epitaxial structure extends in a first direction; the grounding structure wraps one end of the columnar epitaxial structure; the bit line structure wraps the other end of the columnar epitaxial structure; the columnar capacitor structure surrounds the columnar epitaxial structure, and is located between the grounding structure and the bit line structure; and the word line structure surrounds the columnar epitaxial structure, and is located between the bit line structure and the columnar capacitor structure.

Abstract: The present disclosure relates to a memory and a forming method thereof. The method of forming a memory includes: forming a stacked layer on a surface of a substrate, the stacked layer including interlayer isolation layers arranged at intervals in a first direction and a sacrificial layer group located between adjacent two of the interlayer isolation layers, the sacrificial layer group including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer sequentially stacked in the first direction, and the stacked layer including a transistor region, where the first direction is a direction perpendicular to a top surface of the substrate; removing the first sacrificial layer in the transistor region to form a first gap; forming an active pillar in the first gap; removing the second sacrificial layer and the third sacrificial layer in the transistor region to form a second gap.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; a bit line; a word line; an active pillar, wherein the active pillar includes a source region, a channel region, and a drain region, the bit line is connected to one of the source region and the drain region of the active pillar, and the word line surrounds the channel region of the active pillar; a plurality of memory structures, wherein the memory structure is located between adjacent isolation layers, the memory structure includes a first electrode plate, a medium layer, and a second electrode plate that are sequentially stacked, the medium layer is located between the first electrode plate and the second electrode plate, the first electrode plate is connected to the other of the source region and the drain region of the active pillar.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base and a bit line that extends along a first direction; active structures, wherein the active structure includes at least two active layers arranged at intervals, the active layer includes a first source-drain region, a channel region, a second source-drain region, and a support region, and the bit line is connected to the first source-drain region; a word line extending along a second direction, wherein the word line is connected to an adjacent active structure, and the word line surrounds at least two channel regions included in the connected active structure; and a memory structure perpendicularly stacked on the base, where the memory structure is connected to the second source-drain region, and the memory structure surrounds the support region.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The method includes: providing a substrate, wherein the substrate includes a word line region, a bit line region, and a capacitive region arranged adjacently; forming a first stacked structure that covers a surface of the substrate, wherein the first stacked structure includes a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on a surface of the first sacrificial layer; forming a second stacked structure that covers a surface of the first stacked structure, wherein the second stacked structure includes a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on a surface of the second sacrificial layer; and performing an ion implantation on the first semiconductor layer and the second semiconductor layer.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a method of manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a base, and forming active layers and sacrificial layers on the base, wherein two adjacent ones of the active layers constitute an active group, there is a first distance between the active layers in the active group, there is a second distance between adjacent ones of active groups, and the first distance is greater than the second distance; forming isolation layers, wherein each isolation layer penetrates through all the active layers and all the sacrificial layers, and the isolation layers divide each of the active layers into a plurality of active structures; removing a part of the isolation layers in the word line region and a part of the sacrificial layers located in the word line region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate and an active pillar located above the substrate. The active pillar extends in a first direction. The first direction is parallel to a plane where the substrate is located. The active pillar includes a body area extending in the first direction and a peripheral area surrounding the body area. The peripheral area includes a channel area. A type of doped ions of the channel area is the same as a type of doped ions of the body area, and a doping concentration of the channel area is greater than a doping concentration of the body area.

Abstract: The present disclosure relates to a memory structure and a manufacturing method thereof, and a semiconductor structure. The semiconductor structure includes an epitaxial structure, a grounding structure, a columnar capacitor structure, a bit line structure, and a word line structure. The grounding structure wraps one end of the epitaxial structure in a first direction; the columnar capacitor structure wraps the other end of the epitaxial structure in the first direction; the bit line structure surrounds the epitaxial structure, and is located between the grounding structure and the columnar capacitor structure; and the word line structure surrounds the epitaxial structure, and is located between the bit line structure and the columnar capacitor structure.

Abstract: Embodiments provide a method for fabricating a semiconductor device and a semiconductor device structure, and relates to the field of ion implantation technology. A method for fabricating a semiconductor device includes: providing a substrate; forming an active layer on a side of the substrate; forming, on a side of the active layer away from the substrate, a shielding layer covering the active layer; and performing ion implantation of a first element above the shielding layer to form a heavily doped layer on a surface of the active layer. An implantation depth corresponding to a peak implantation concentration of the first element is equal to a thickness of the shielding layer. The heavily doped layer can reduce an oxidation rate of the active layer to a certain extent, thereby improving yield of the semiconductor device.

Abstract: A testing device for testing an antenna is provided. The testing device includes a housing, an antenna module for holding the antenna and disposed under the housing, and a receiving module disposed on the housing. The antenna module includes a base and a flexible film disposed on the base. The receiving module includes a substrate, a coupling radiation element disposed on the substrate and a support disposed on the substrate and having an opening. The antenna is partially exposed from the opening.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.