Patents by Inventor Yi Tang

Yi Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230333150
    Abstract: A testing device for testing an antenna is provided. The testing device includes a housing, an antenna module for holding the antenna and disposed under the housing, and a receiving module disposed on the housing. The antenna module includes a base and a flexible film disposed on the base. The receiving module includes a substrate, a coupling radiation element disposed on the substrate and a support disposed on the substrate and having an opening. The antenna is partially exposed from the opening.
    Type: Application
    Filed: June 22, 2023
    Publication date: October 19, 2023
    Inventors: Chi-Chang LAI, Kai-Yi TANG, Mill-Jer WANG
  • Patent number: 11784183
    Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Tang Lin, Clement Hsingjen Wann, Neng-Kuo Chen
  • Publication number: 20230299203
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: May 24, 2023
    Publication date: September 21, 2023
    Inventors: Shao-Ming YU, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Publication number: 20230297208
    Abstract: A computing system receives position data from each of a plurality of user computing devices, the position data indicating a cursor position on a collaborative user interface for each collaborator during a collaborative session. The system determines, based on the position data, whether the cursor position of a respective collaborator is within a bounding area of a widget presented on the collaborative user interface. When the cursor position of the respective collaborator is within the bounding area of the widget, the system transmits feedback response data to each of the plurality of user computing devices to cause a corresponding feedback response for the widget to be presented on the collaborative user interface displayed on each of the plurality of user computing devices.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 21, 2023
    Inventors: Bersabel Tadesse, Sawyer Hood, Yi Tang Jackie Chui, Michael Yong
  • Publication number: 20230258883
    Abstract: An optical module includes a light emitting assembly. The light emitting assembly includes a plurality of lasers, a plurality of wavelength division multiplexers and a lens group. The plurality of lasers emit a plurality of optical signals. The plurality of wavelength division multiplexers multiplex the plurality of optical signals into a plurality of composite optical signals. The lens group includes a first lens, a second lens, and a third lens. The second lens is configured to transmit a first part of the plurality of composite optical signals exited from the first lens, reflect a second part of the plurality of composite optical signals exited from the third lens to the first lens, and transmit the second part of the plurality of composite optical signals reflected by the first lens, so as to multiplex the plurality of composite optical signals into the merge composite optical signal.
    Type: Application
    Filed: March 16, 2023
    Publication date: August 17, 2023
    Applicant: HISENSE BROADBAND MULTIMEDIA TECHNOLOGIES CO., LTD.
    Inventors: Honghao ZHANG, Xujie HUANG, Shuhua YE, Bin WANG, Jiaao ZHANG, Xueru LIU, Qinhao FU, Yifan XIE, Yi TANG, Benzheng DONG
  • Patent number: 11726122
    Abstract: A testing device for testing an antenna is provided. The testing device includes a housing, an antenna module, and a receiving module. The antenna module is used for holding the antenna and disposed on the housing, wherein the antenna is coupled to an antenna testing apparatus. The receiving module is disposed on the housing and includes a coupling radiation element physically separated from the antenna, wherein the receiving module is configured to receive an excited signal emitted from the antenna.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Chang Lai, Kai-Yi Tang, Mill-Jer Wang
  • Patent number: 11721761
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: August 8, 2023
    Assignee: Mosaid Technologies Incorporated
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Publication number: 20230228955
    Abstract: An optical module includes a light receiving assembly and a first fiber optic adapter. The light receiving assembly includes a first lens group, a plurality of wavelength division demultiplexers and at least one light receiving component. The first lens group is configured to split optical signals transmitted to the first cavity body for a first time according to a wavelength to obtain a first optical signal beam and a second optical signal beam. The plurality of wavelength division demultiplexers include a first wavelength division demultiplexer and a second wavelength division demultiplexer. The first wavelength division demultiplexer is configured to split the first optical signal beam for a second time according to a wavelength. The second wavelength division demultiplexer is configured to split the second optical signal beam for a second time according to a wavelength. The light receiving component includes a plurality of light receiving chips.
    Type: Application
    Filed: March 16, 2023
    Publication date: July 20, 2023
    Applicant: HISENSE BROADBAND MULTIMEDIA TECHNOLOGIES CO., LTD.
    Inventors: Honghao ZHANG, Jiaao ZHANG, Bin WANG, Xujie HUANG, Shuhua YE, Xueru LIU, Qinhao FU, Yifan XIE, Yi TANG, Benzheng DONG
  • Publication number: 20230209767
    Abstract: In one embodiment, an apparatus includes an enclosure configured for connection to a printed circuit board, a substrate within the enclosure, a plurality of components mounted on the substrate, a fluid inlet connector, a fluid outlet connector, and a plurality of flow channels within the enclosure, at least one of the components disposed in each the flow channels and segregated from other components in another of the flow channels. The enclosure is configured for immersion cooling of the components.
    Type: Application
    Filed: March 6, 2023
    Publication date: June 29, 2023
    Inventors: M. Baris Dogruoz, Mark Nowell, Yi Tang, Rakesh Chopra, Mandy Hin Lam
  • Publication number: 20230186684
    Abstract: Disclosed are a method for capturing three dimensional actions of multiple persons, a storage media and an electronic device. The method includes: obtaining synchronous video frames of multiple cameras, recognizing and positioning joint points in each synchronous video frame of each camera, to obtain two dimensional (2D) joint point of each person in each camera; calculating an anti-projection ray of each 2D joint point, and clustering coordinates of two endpoints of a shortest distance between two anti-projection rays to obtain a 2D personnel matching scheme, wherein the anti-projection ray is from a camera pointing to its corresponding 2D joint point; and performing a three dimensional (3D) reconstruction for each person according to the 2D personnel matching scheme, to generate 3D information of each person for capturing 3D actions.
    Type: Application
    Filed: February 9, 2023
    Publication date: June 15, 2023
    Applicant: UNILUMIN GROUP CO., LTD
    Inventors: Youhai QIU, Yi TANG, Qianru XU
  • Patent number: 11647607
    Abstract: In one embodiment, an apparatus includes an enclosure configured for connection to a printed circuit board, a substrate within the enclosure, a plurality of components mounted on the substrate, a fluid inlet connector, a fluid outlet connector, and a plurality of flow channels within the enclosure, at least one of the components disposed in each the flow channels and segregated from other components in another of the flow channels. The enclosure is configured for immersion cooling of the components.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: May 9, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: M. Baris Dogruoz, Mark Nowell, Yi Tang, Rakesh Chopra, Mandy Hin Lam
  • Publication number: 20230123873
    Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Yi-Tang LIN, Clement Hsingjen WANN, Neng-Kuo CHEN
  • Publication number: 20230068410
    Abstract: An integrated application platform enables users to select and implement widgets, in order to insert widget objects with rendered content. The widget objects are persistent content elements that are dynamically responsive to user input. Further, the widget objects are associated with functionality that extends or supplements the functionality provided by the integrated application platform.
    Type: Application
    Filed: August 24, 2022
    Publication date: March 2, 2023
    Inventors: Bersabel Tadesse, Jonas Sicking, Michael Yong, Sawyer Hood, Yi Tang Jackie Chui, Rohit Chouhan
  • Publication number: 20230054620
    Abstract: Disclosed is a microcapsule comprising: (i) a core comprising a benefit agent; and (ii) a shell comprising silica; wherein said shell comprises plate-like inorganic materials having an average thickness of 1-1000 nm; wherein said benefit agent is fragrance, pro-fragrance, hair conditioning agent, anti-dandruff agent, moisturizers, emollients, dyes and/or pigments, colour care additives (including dye fixing agents), or a mixture thereof.
    Type: Application
    Filed: November 3, 2020
    Publication date: February 23, 2023
    Inventors: Xiaoyun PAN, Weizheng ZHOU, Yi TANG, Siqi LEI
  • Publication number: 20230051453
    Abstract: The disclosure provides biosynthetic platforms that generate olivetolic acid and its analogues at high titers from microbes, and in cell free systems.
    Type: Application
    Filed: January 9, 2021
    Publication date: February 16, 2023
    Inventors: Yi Tang, Mengbin Chen, Ikechukwu Okorafor
  • Publication number: 20230045147
    Abstract: The present invention relates to the field of air filtration, in particular to a polytetrafluoroethylene composite filter material. The polytetrafluoroethylene composite filter material comprises a supporting layer and a polytetrafluoroethylene film layer, wherein the supporting layer is a silver-plated carbon nanomaterial-modified meltblown nonwoven fabric. The polytetrafluoroethylene composite filter material is prepared by fiberizing a resin material modified by silver-plated carbon nanomaterial on the surface of a polytetrafluoroethylene film by a melt-blowing method. The polytetrafluoroethylene composite filter material of the present invention combines filtering and sterilizing functions, has higher filtering efficiency and filtering precision, has the functions of sterilizing and killing viruses, has a good isolation effect, and greatly prolongs the service life of the filter material.
    Type: Application
    Filed: August 24, 2020
    Publication date: February 9, 2023
    Inventors: Ping XIAO, Zhongliang XIAO, Chunyang CAI, Yi TANG, Hui LI, Jian SU
  • Publication number: 20230013060
    Abstract: Embodiments relate to a semiconductor device and a forming method. The semiconductor device includes: a substrate; a memory array positioned on the substrate and at least including memory cells spaced along a first direction, each of the memory cells including a transistor, the transistor including a gate electrode, channel regions distributed on two opposite sides of the gate electrode along a third direction, and a source region and a drain region distributed on two opposite sides of each of the channel regions along a second direction, the first direction and the third direction being directions parallel to a top surface of the substrate, the first direction intersecting with the third direction, and the second direction being a direction perpendicular to the top surface of the substrate; and a word line extending along the first direction and continuously electrically connected to the gate electrodes spaced along the first direction.
    Type: Application
    Filed: September 25, 2022
    Publication date: January 19, 2023
    Inventors: Mengmeng YANG, Yi TANG
  • Publication number: 20230014052
    Abstract: A method for forming a semiconductor structure includes the following: a substrate is provided, the substrate including a first area and a second area arranged in sequence in a second direction and T-shaped active pillars located in the first area and the second area and arranged in an array in a first direction and a third direction, the first, second and third directions being perpendicular to one another, and the first and second directions being parallel to a surface of the substrate; T-shaped gate structures located on surfaces of the T-shaped active pillars and bit line structures extending in the third direction are formed in the first area, a plurality of T-shaped gate structures located in the first direction being interconnected; and capacitor structures extending in the second direction is formed in the second area, the bit line structures and the capacitor structures being connected to the T-shaped gate structures.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 19, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yi TANG
  • Publication number: 20230017086
    Abstract: Embodiments of the disclosure provide a semiconductor substrate, a method for forming same, and a layout structure. The method includes: providing a semiconductor structure including a first region and a second region arranged in sequence along a second direction, the second region including active structures arranged in an array along a first direction and a third direction, each of the active structure at least including a channel structure, the first direction, the second direction, and the third direction being perpendicular to each other, and the first direction and the second direction being parallel to a surface of the semiconductor substrate; forming a gate structure on a surface of the channel structure; and forming a word line structure extending in the first direction on the first region. The word line structure is connected with the gate structure located on the same layer.
    Type: Application
    Filed: September 28, 2022
    Publication date: January 19, 2023
    Inventors: Xiaojie LI, Daohuan FENG, Meng HUANG, Yi TANG
  • Publication number: 20230012587
    Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor structure, including a substrate and connection lines. Structural cells arranged in an array are provided on the substrate, and include transistor groups arranged in a first direction, and the transistor groups include multi-layer transistors extending in a second direction. The first direction is perpendicular to the second direction, and both are parallel to a surface of the substrate. The structural cells further include bit lines extending in a third direction, the bit lines are electrically connected to the multi-layer transistors in the same transistor group, where the third direction is perpendicular to the surface of the substrate. The connection lines are connected to the bit lines in the structural cells in one-to-one correspondence, and one bit line in the structural cells arranged in the array is connected to the same connection line.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 19, 2023
    Inventors: Yi TANG, Jianfeng XIAO, Xiaojie LI