Abstract: Embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The method includes: providing a semiconductor substrate including a plurality of active pillars arranged at intervals; etching the active pillar to form an annular groove, in which the annular groove does not expose a top surface and a bottom surface of the active pillar; and forming a first semiconductor layer in the annular groove to form the semiconductor structure; in which a band gap of the first semiconductor layer is smaller than a band gap of the active pillar.

Abstract: Provide is a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method includes the following operations. A substrate is provided. Multiple silicon pillars are formed in the substrate, and extend along a first direction. In the first direction, each of the silicon pillars includes a first portion and a second portion. An insulating layer is formed in the second portion of the silicon pillar. A conductive layer is formed in the first portion of the silicon pillar. A capacitor layer is formed on surfaces of the insulating layer and the conductive layer of the silicon pillar.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, at least a gate structure, a first dielectric layer covering a surface of the substrate and the gate structure being formed on the substrate, and a first dielectric layer on a side surface of the gate structure serving as a first sidewall; forming a sacrificial sidewall on a side surface of the first sidewall; removing the sacrificial sidewall after a first doped region and a second doped region are respectively formed in the substrate on both sides of the sacrificial sidewall; forming a second sidewall on a side surface of the first sidewall.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Abstract: The present disclosure provides compositions and methods for treating a disease or condition in a subject in need thereof, comprising administering to the subject a pharmaceutically effective amount of a composition comprising a plurality of particles comprising at least one therapeutic biologic suspended in a pharmaceutically acceptable liquid carrier.

Abstract: A method for forming an interconnect structure is described. In some embodiments, the method includes forming a mask structure on a dielectric layer, and the mask structure includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method further includes forming first openings having first dimensions in the first layer and forming a multilayer structure over the first layer. The multilayer structure includes a bottom layer disposed in the first openings and over the first layer, a middle layer disposed on the bottom layer, and a photoresist layer disposed on the middle layer. The method further includes forming second openings having second dimensions in the bottom layer to expose portions of the dielectric layer, and the second dimensions are smaller than the first dimensions. The method further includes extending the second openings into the dielectric layer.

Abstract: A speech processing apparatus applied in a communication device having a mechanical defect is disclosed. The apparatus comprises an acoustic echo cancellation (AEC) unit, a multiplier and a processor. The AEC unit cancels an echo in a first audio signal from a microphone using a known AEC algorithm to generate a second audio signal. The multiplier multiplies corresponding M frames of a downlink audio signal by a gain to provide a gained downlink signal for a speaker. The processor performs operations comprising: muting an uplink audio signal when a first power level for M frames of a first input signal is less than a first threshold value; and, reducing the gain when the first power level and a second power level for M frames of a second input signal are respectively greater than the first threshold value and a second threshold value.

Abstract: Optical signal to noise ratios that more accurately characterize optical link noise are determined. As noise induced by an optical receiver does not generally vary with an input optical signal power, a power of an incoming optical signal is varied at the receiver. A resulting variation in noise measure represents a variation in link noise and does not include any variation caused by receiver noise, as receiver noise does not generally vary with optical signal power. Thus, the contribution of optical link noise can be discerned from other noise induced by the receiver itself. A more accurate characterization of optical link performance is thus provided.

Abstract: Optical signal to noise ratios that more accurately characterize optical link noise are determined. As noise induced by an optical receiver does not generally vary with an input optical signal power, a power of an incoming optical signal is varied at the receiver. A resulting variation in noise measure represents a variation in link noise and does not include any variation caused by receiver noise, as receiver noise does not generally vary with optical signal power. Thus, the contribution of optical link noise can be discerned from other noise induced by the receiver itself. A more accurate characterization of optical link performance is thus provided.

Abstract: Single-module nonribosomal peptide synthetases (NRPSs) and NRPS-like enzymes activate and transform carboxylic acids in both primary and secondary metabolism; and are of great interest due to their biocatalytic potentials. The single-module NRPS IvoA is essential for fungal pigment biosynthesis. As disclosed herein, we show that IvoA catalyzes ATP-dependent unidirectional stereoinversion of L-tryptophan to D-tryptophan with complete conversion. While the stereoinversion is catalyzed by the epimerization (E) domain, the terminal condensation (C) domain stereoselectively hydrolyzes D-tryptophanyl-S-phosphopantetheine thioester and thus represents a noncanonical C domain function. Using IvoA, we demonstrate a biocatalytic stereoinversion/deracemization route to access a variety of substituted D-tryptophan analogs in high enantiomeric excess.

Abstract: The present disclosure provides compositions and methods for treating a disease or condition in a subject in need thereof, comprising administering to the subject a pharmaceutically effective amount of a composition comprising a plurality of particles comprising at least one therapeutic biologic suspended in a pharmaceutically acceptable liquid carrier.

Abstract: A method for transferring a container configured to hold at least one article used in semiconductor fabrication is provided. The method includes moving a transferring mechanism to a first position that is adjacent to the original space; producing an image of an edge of the container that is adjacent to the original space using an optical receiver before the container is moved to a destination space; and performing an image analysis of the image to determine whether to move the container to the destination space.

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: Glutamine synthetase mutant having glufosinate ammonium resistance, application thereof and a cultivation method therefor. Comparing with the reference sequence, the amino acid sequence of the glutamine synthetase mutant has one or a combination of the following mutations: (1) the amino acid of the glutamine synthetase mutant corresponding to amino acid site 59 of the reference sequence is mutated to X1, wherein X1=A, C, D, E, F, G, H, I, K, P, T, V or Y; (2) the amino acid of the glutamine synthetase mutant corresponding to amino acid site 296 of the reference sequence is mutated to X2, wherein X2=A, D, E, G, I, K, M, P, Q, R, S, T, or V.

Abstract: In one embodiment, an apparatus includes an enclosure configured for connection to a printed circuit board, a substrate within the enclosure, a plurality of components mounted on the substrate, a fluid inlet connector, a fluid outlet connector, and a plurality of flow channels within the enclosure, at least one of the components disposed in each the flow channels and segregated from other components in another of the flow channels. The enclosure is configured for immersion cooling of the components.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: An alkaline cleaning composition is provided. The alkaline cleaning composition includes an alkaline compound, 5% to 40% by weight of propylene glycol monomethyl ether, 10% to 30% by weight of water, and a polar solvent. Wherein, the polar solvent includes acetals, glycol ethers, pyrrolidones, or a combination thereof, and the alkaline cleaning composition is free of benzenesulfonic acid.

Abstract: An electronic device includes a motherboard, a bridging device, and an add-in card. The motherboard includes a processor, a first circuit board, and a first connector. The processor is coupled to the first connector through the first circuit board. The bridging device includes a second circuit board and a second connector and is disposed on the motherboard and coupled to the first connector. The second connector is coupled to the first connector through the second circuit board. The add-in card includes a third circuit board and a peripheral circuit and is disposed on the bridging device and coupled to the second connector. The peripheral circuit is coupled to the second connector through the third circuit board. The processor is coupled to the peripheral circuit through a signal path including the first circuit board, the first connector, the second circuit board, the second connector, and the third circuit board.

Abstract: Embodiments of the present application relate to the communications field and disclose a calibration method and a communications device, capable of compensating for measured amplitude and phase results. The method includes determining a position error of each of the N antenna groups, and then determining an actual position of the antenna group based on a target position of the antenna group and the position error of the antenna group. A phase compensation value and/or an amplitude compensation value of the antenna group are determined for a target probe of the second device based on the actual position of the antenna group. Based on the phase compensation value and/or the amplitude compensation value of the antenna group, compensating is performed for a phase result and/or an amplitude result that are/is obtained by the target probe of the second device by measuring a signal transmitted by the antenna group.