Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Abstract: One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.

Abstract: A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.

Abstract: A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the channel material is different from the lattice constant of the bulk substrate to introduce strain to the channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOT substrate is included.

Abstract: One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: A method includes providing a first substrate having first and second regions, fabricating over the first region of the first substrate a channel of a first transistor, providing a second substrate over the second region of the first substrate, fabricating over the second substrate a channel of a second transistor, and forming gates respectively and simultaneously over the channels of the first and second transistors.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer is formed on a substrate and includes a first semiconductor device, the first semiconductor device including a first electrode structure. The second device layer is formed on the first device layer and includes a second semiconductor device, the second semiconductor device including a second electrode structure. The first inter-level connection structure includes one or more first conductive materials and is configured to electrically connect to the first electrode structure and the second electrode structure.

Abstract: A method includes forming an isolation feature in a semiconductor substrate; forming a first fin-like active region and a second fin-like active region in the semiconductor substrate and interposed by the isolation feature; forming a dummy gate stack on the isolation feature, wherein the dummy gate extends to the first fin-like active region from one side and to the second fin-like active region from another side.

Abstract: A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.

Abstract: One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.

Abstract: A semiconductor structure having multiple semiconductor-device layers is provided. The semiconductor structure includes a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide. The first semiconductor device layer comprises a patterned top surface. A blanket layer of uniform material composition includes insulator material is fabricated over the patterned top surface. The semiconductor structure further includes a second buried oxide bonded to the blanket layer and a second semiconductor device layer fabricated above the second buried oxide.

Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOT”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOT substrate is included.