Abstract: A bipolar junction transistor (BJT) formed using a fin field-effect transistor (FinFET) complimentary metal-oxide-semiconductor (CMOS) process flow is provided. The BJT includes an emitter fin, a base fin, and a collector fin formed on a substrate. The base fin encloses the emitter fin and collector fin encloses the emitter fin. In some embodiments, the emitter fin, base fin, and collector fin have a square shape when viewed from above and are concentric with each other.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A method of fabricating a Fin field effect transistor (FinFET) includes providing a substrate having a first fin and a second fin extending above a substrate top surface, wherein the first fin has a top surface and sidewalls and the second fin has a top surface and sidewalls. The method includes forming an insulation layer between the first and second fins. The method includes forming a first gate dielectric having a first thickness covering the top surface and sidewalls of the first fin using a plasma doping process. The method includes forming a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness. The method includes forming a conductive gate strip traversing over both the first gate dielectric and the second gate dielectric.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.

Abstract: An aspect of the instant disclosure provides a multilayer device structure that comprises: a substrate defining a first device region and a second device region laterally offsetting each other; a first channel material layer disposed over the substrate in the first device region; a second channel material layer over the substrate in the second device region, wherein the second channel material layer is arranged at an elevation higher than the first channel material layer; and a first device and a second device respectively fabricated from the first and the second channel material layers, wherein the first device and the second device vertically offsetting each other and defining an offset region above the first device, thereby reducing parasitic interference there-between.

Abstract: One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.

Abstract: A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material. The model is used to estimate the height of an epitaxially grown semiconductor material in the other semiconductor devices.

Abstract: A method of fabricating a Fin field effect transistor (FinFET) includes providing a substrate having a first fin and a second fin extending above a substrate top surface, wherein the first fin has a top surface and sidewalls and the second fin has a top surface and sidewalls. The method includes forming an insulation layer between the first and second fins. The method includes forming a first gate dielectric having a first thickness covering the top surface and sidewalls of the first fin using a plasma doping process. The method includes forming a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness. The method includes forming a conductive gate strip traversing over both the first gate dielectric and the second gate dielectric.

Abstract: A multilayer semiconductor structure having a layout footprint with a first region and a non-overlapping second region and different transistor types fabricated using different channel material. The semiconductor structure comprises a first transistor layer comprising a first type of channel material in the first region but no channel material in the second region. The semiconductor structure further comprises a second transistor layer comprising a second type of channel material in the second region but no channel material in the first region. The second transistor layer is vertically elevated above the first transistor layer. A first transistor is fabricated on the first transistor layer. A second transistor is fabricated on the second transistor layer, and the first transistor is interconnected with the second transistor to form a circuit.

Abstract: A semiconductor device structure and a method of fabricating a semiconductor device structure are provided. A first device layer is formed over a substrate, where an alignment structure is patterned in the first device layer. A dielectric layer is provided over the first device layer. The dielectric layer is patterned to include an opening over the alignment structure. A second device layer is formed over the dielectric layer. The second device layer is patterned using a mask layer, where the mask layer includes a structure that is aligned relative to the alignment structure. The alignment structure is visible via the opening during the patterning of the second device layer.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer and a second device layer formed on a first device layer. The first device layer is formed on a substrate and includes a first channel structure configured to conduct a first current, the first channel structure including a first material capable of sustaining a first processing temperature. The second device layer includes a second channel structure configured to conduct a second current, the second channel structure including a second material capable of sustaining a second processing temperature, the second processing temperature being equal to or lower than the first processing temperature.

Abstract: A bipolar junction transistor (BJT) formed using a fin field-effect transistor (FinFET) complimentary metal-oxide-semiconductor (CMOS) process flow is provided. The BJT includes an emitter fin, a base fin, and a collector fin formed on a substrate. The base fin encloses the emitter fin and collector fin encloses the emitter fin. In some embodiments, the emitter fin, base fin, and collector fin have a square shape when viewed from above and are concentric with each other.

Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.

Abstract: Systems and methods are provided for dopant activation in a semiconductor structure for fabricating semiconductor devices. For example, a substrate is provided. A semiconductor structure is formed on the substrate. Pre-amorphization implantation is performed on the semiconductor structure. Microwave radiation is applied to the semiconductor structure to activate dopants in the semiconductor structure for fabricating semiconductor devices. Microwave-radiation absorption of the semiconductor structure is increased after the pre-amorphization implantation.

Abstract: A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Abstract: A bipolar junction transistor (BJT) formed using a fin field-effect transistor (FinFET) complimentary metal-oxide-semiconductor (CMOS) process flow is provided. The BJT includes an emitter fin, a base fin, and a collector fin formed on a substrate. The base fin encloses the emitter fin and collector fin encloses the emitter fin. In some embodiments, the emitter fin, base fin, and collector fin have a square shape when viewed from above and are concentric with each other.

Abstract: A method of fabricating a Fin field effect transistor (FinFET) includes providing a substrate having a first fin and a second fin extending above a substrate top surface, wherein the first fin has a top surface and sidewalls and the second fin has a top surface and sidewalls. The method includes forming an insulation layer between the first and second fins. The method includes forming a first gate dielectric having a first thickness covering the top surface and sidewalls of the first fin using a plasma doping process. The method includes forming a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness. The method includes forming a conductive gate strip traversing over both the first gate dielectric and the second gate dielectric.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer and a second device layer formed on a first device layer. The first device layer is formed on a substrate and includes a first channel structure configured to conduct a first current, the first channel structure including a first material capable of sustaining a first processing temperature. The second device layer includes a second channel structure configured to conduct a second current, the second channel structure including a second material capable of sustaining a second processing temperature, the second processing temperature being equal to or lower than the first processing temperature.

Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included.