Patents by Inventor Yi-Tang LIN
Yi-Tang LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140331193Abstract: A semiconductor manufacturing method of generating a layout for a device includes defining a first plurality of mandrels in a first active region of a first layout. Each mandrel of the first plurality of mandrels extends in a first direction and being spaced apart in a second direction perpendicular to the first direction. The method further includes defining a second plurality of mandrels in a second active region of the first layout. Each mandrel of the second plurality of mandrels extends in the first direction and being spaced apart in the second direction. An edge of the first active region is spaced from an edge of the second active region by a minimum distance less than a specified minimum spacing. The method further includes connecting, using a layout generator, at least one mandrel of the first plurality of mandrels to a corresponding mandrel of the second plurality of mandrels.Type: ApplicationFiled: July 17, 2014Publication date: November 6, 2014Inventors: Chien-Hsun WANG, Chih-Sheng CHANG, Yi-Tang LIN, Ming-Feng SHIEH
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Patent number: 8881066Abstract: Methods for forming a single fin fin-like field effect transistor (FinFET) device are disclosed. An exemplary method includes providing a main mask layout and a trim mask layout to form fins of a fin-like field effect transistor (FinFET) device, wherein the main mask layout includes a first masking feature and the trim mask layout includes a second masking feature that defines at least two fins, the first masking feature and the second masking feature having a spatial relationship; and modifying the main mask layout based on the spatial relationship between the first masking feature and the second masking feature, wherein the modifying the main mask layout includes modifying the first masking feature such that a single fin FinFET device is formed using the modified main mask layout and the trim mask layout.Type: GrantFiled: December 29, 2011Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Yi-Tang Lin, Chia-Cheng Ho, Chih-Sheng Chang
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Patent number: 8875076Abstract: A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.Type: GrantFiled: March 28, 2014Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tang Lin, Cheok-Kei Lei, Shu-Yu Chen, Yu-Ning Chang, Hsiao-Hui Chen, Chih-Sheng Chang, Chien-Wen Chen, Clement Hsingjen Wann
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Publication number: 20140239414Abstract: A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.Type: ApplicationFiled: April 22, 2014Publication date: August 28, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Ho, Tzu-Chiang Chen, Yi-Tang Lin, Chih-Sheng Chang
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Patent number: 8816444Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.Type: GrantFiled: March 9, 2012Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh, Ting-Chu Ko, Chung-Hsien Chen
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Patent number: 8806397Abstract: A method of generating a layout for a device includes receiving a first layout including a plurality of active regions, each active region of the plurality of active regions having sides. The method further includes defining a plurality of elongate mandrels that each extend in a first direction and are spaced apart from one another in a second direction perpendicular to the first direction. The method further includes for each adjacent pair of partially-parallel active regions of the plurality of active regions having a minimum distance less than a specified minimum spacing, connecting at least a portion of nearest ends of pairs of elongate mandrels, each mandrel of a pair from a different active region. The method further includes generating a second layout including a plurality of elongate mandrels in the plurality of active regions, and connective elements between active regions of at least one adjacent pair of active regions.Type: GrantFiled: September 4, 2013Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh
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Patent number: 8799833Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.Type: GrantFiled: March 9, 2012Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh
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Publication number: 20140215420Abstract: A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.Type: ApplicationFiled: March 28, 2014Publication date: July 31, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Tang LIN, Cheok-Kei LEI, Shu-Yu CHEN, Yu-Ning CHANG, Hsiao-Hui CHEN, Chih-Sheng CHANG, Chien-Wen CHEN, Clement Hsingjen WANN
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Patent number: 8769446Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. A plurality of elongate mandrels is defined in a plurality of active regions. Where adjacent active regions are partially-parallel and within a specified minimum spacing, connective elements are added to a portion of the space between the adjacent active regions to connect the mandrel ends from one active region to another active region.Type: GrantFiled: September 8, 2011Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh
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Patent number: 8759184Abstract: A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.Type: GrantFiled: January 9, 2012Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Ho, Tzu-Chiang Chen, Yi-Tang Lin, Chih-Sheng Chang
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Patent number: 8726220Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.Type: GrantFiled: March 9, 2012Date of Patent: May 13, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tang Lin, Cheok-Kei Lei, Shu-Yu Chen, Yu-Ning Chang, Hsiao-Hui Chen, Chih-Sheng Chang, Chien-Wen Chen, Clement Hsingjen Wann
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Patent number: 8633076Abstract: A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.Type: GrantFiled: November 23, 2010Date of Patent: January 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Yi-Tang Lin
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Publication number: 20140013288Abstract: A method of generating a layout for a device includes receiving a first layout including a plurality of active regions, each active region of the plurality of active regions having sides. The method further includes defining a plurality of elongate mandrels that each extend in a first direction and are spaced apart from one another in a second direction perpendicular to the first direction. The method further includes for each adjacent pair of partially-parallel active regions of the plurality of active regions having a minimum distance less than a specified minimum spacing, connecting at least a portion of nearest ends of pairs of elongate mandrels, each mandrel of a pair from a different active region. The method further includes generating a second layout including a plurality of elongate mandrels in the plurality of active regions, and connective elements between active regions of at least one adjacent pair of active regions.Type: ApplicationFiled: September 4, 2013Publication date: January 9, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Hsun WANG, Chih-Sheng CHANG, Yi-Tang LIN, Ming-Feng SHIEH
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Patent number: 8621406Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.Type: GrantFiled: March 9, 2012Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheok-Kei Lei, Yi-Tang Lin, Hsiao-Hui Chen, Yu-Ning Chang, Shu-Yu Chen, Chien-Wen Chen, Chih-Sheng Chang, Clement Hsingjen Wann
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Publication number: 20130334615Abstract: A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region.Type: ApplicationFiled: June 10, 2013Publication date: December 19, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Ho, Tzu-Chiang Chen, Yi-Tang Lin, Chih-Sheng Chang
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Patent number: 8609499Abstract: A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region.Type: GrantFiled: January 9, 2012Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Ho, Tzu-Chiang Chen, Yi-Tang Lin, Chih-Sheng Chang
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Patent number: 8525267Abstract: A semiconductor FinFET device includes a plurality of gate lines formed in a first direction, and two types of fin structures. A first type of fin structures is formed in a second direction, and a second type of fin structures formed perpendicular to the first type of fin structures. A contact hole couples to one or more of the second type of fin structures.Type: GrantFiled: November 23, 2010Date of Patent: September 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh
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Publication number: 20130187237Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.Type: ApplicationFiled: January 23, 2012Publication date: July 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD,Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
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Publication number: 20130175638Abstract: A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region.Type: ApplicationFiled: January 9, 2012Publication date: July 11, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Ho, Tzu-Chiang Chen, Yi-Tang Lin, Chih-Sheng Chang
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Publication number: 20130175584Abstract: A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.Type: ApplicationFiled: January 9, 2012Publication date: July 11, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Ho, Tzu-Chiang Chen, Yi-Tang Lin, Chih-Shen Chang