Abstract: A bipolar junction transistor (BJT) formed using a fin field-effect transistor (FinFET) complimentary metal-oxide-semiconductor (CMOS) process flow is provided. The BJT includes an emitter fin, a base fin, and a collector fin formed on a substrate. The base fin encloses the emitter fin and collector fin encloses the emitter fin. In some embodiments, the emitter fin, base fin, and collector fin have a square shape when viewed from above and are concentric with each other.

Abstract: Methods for forming a single fin fin-like field effect transistor (FinFET) device are disclosed. An exemplary method includes providing a main mask layout and a trim mask layout to form fins of a fin-like field effect transistor (FinFET) device, wherein the main mask layout includes a first masking feature and the trim mask layout includes a second masking feature that defines at least two fins, the first masking feature and the second masking feature having a spatial relationship; and modifying the main mask layout based on the spatial relationship between the first masking feature and the second masking feature, wherein the modifying the main mask layout includes modifying the first masking feature such that a single fin FinFET device is formed using the modified main mask layout and the trim mask layout.

Abstract: A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material. The model is used to estimate the height of an epitaxially grown semiconductor material in the other semiconductor devices.

Abstract: The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric.

Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.

Abstract: System and method for hierarchy reconstruction from a flattened layout are described. In one embodiment, a method for producing a reconstructed layout for an integrated circuit design from an original layout and a revised layout includes, for each pattern of the original layout, determining a pattern of the revised layout that corresponds to the pattern of the original layout; and assigning the corresponding pattern of the revised layout to a temporary instance, the temporary instance corresponding to an instance of the pattern of the original layout and citing to a temporary cell. The method further includes creating a temporary reconstructed layout from the temporary instances; and producing the reconstructed layout from the temporary reconstructed layout, wherein a hierarchy of the reconstructed layout is similar to a hierarchy of the original layout.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.

Abstract: A semiconductor FinFET device includes a plurality of gate lines formed in a first direction, and two types of fin structures. A first type of fin structures is formed in a second direction, and a second type of fin structures formed perpendicular to the first type of fin structures. A contact hole couples to one or more of the second type of fin structures.

Abstract: A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. A plurality of elongate mandrels is defined in a plurality of active regions. Where adjacent active regions are partially-parallel and within a specified minimum spacing, connective elements are added to a portion of the space between the adjacent active regions to connect the mandrel ends from one active region to another active region.