Abstract: A mechanism for building decentralized computer applications that execute on a distributed computing system. The present technology works within a web browser, client application, or other software and provides access to decentralized computer applications through the browser. The present technology is non-custodial, wherein a public-private key pair, which represents user identity, is created on a client machine and then directly encrypted by a third-party platform without relying on one centralized computing system.

Abstract: At least one isolated lactic acid bacteria strains selected from the following: TSP05 (Lactobacillus plantarum), TSF331 (Lactobacillus fermentum) and TSR332 (Lactobacillus reuteri) is provided. The above-mentioned active or inactive lactic acid bacteria strains have a function of hepatoprotection and is used in a form of a food composition or a pharmaceutical composition.

Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.

Abstract: A battery pack, comprising a first cell and a second cell connected in series, the first cell having a current cut-off device and having a first failure voltage, the current cut-off device being configured to be able to break a circuit in response to a voltage value of the first cell reaching or exceeding the first failure voltage, and the second cell having no current cut-off device. The battery pack may use a soft pack battery as the second cell, having advantages such as high energy density, low impedance, high discharge power, a low rate of temperature rise during high-rate discharge, and flexibility in dimensions.

Abstract: Provided are a circuit apparatus, a manufacturing method thereof, and a circuit system. The circuit apparatus includes a flexible circuit board, a flexible packaging material layer and an electronic device. The flexible circuit board has at least one hollow pattern, wherein the flexible circuit board has an inner region and a peripheral region surrounding the inner region, and has a first surface and a second surface opposite to each other. The flexible packaging material layer is disposed in the at least one hollow pattern. The electronic device is disposed on the first surface of the flexible circuit board and electrically connected with the flexible circuit board.

Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A method includes, during a processing cycle: navigating the sanding head across a region of a workpiece according to a toolpath; and, based on a sequence of force values output by a force sensor coupled to the sanding head, deviating the sanding head from the toolpath to maintain forces of the sanding head on the workpiece region proximal a target force. The method also includes: detecting a sequence of positions of the sanding head traversing the workpiece region; interpreting a surface contour in the workpiece region based on the sequence of positions; detecting a difference between the surface contour and a corresponding target surface defined in a target model of the workpiece; generating a second toolpath for the workpiece region based on the difference; and, during a second processing cycle, navigating the sanding head across the workpiece region according to the second toolpath to reduce the difference.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.

Abstract: A semiconductor device is provided. The semiconductor device includes a waveguide over a substrate. The semiconductor device includes a first dielectric structure over the substrate, wherein a portion of the waveguide is in the first dielectric structure. The semiconductor device includes a second dielectric structure under the waveguide, wherein a first sidewall of the second dielectric structure is adjacent a first sidewall of the substrate.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.