Abstract: The present disclosure provides a display device. The display device includes a substrate, a pixel array, a circuit bridge structure, a first trace region, a second trace region, and a display film layer. The pixel array is located on the substrate. The circuit bridge structure is located at one side of the pixel array. The first trace region is located between the pixel array and a first side of the circuit bridge structure. The second trace region is located at a second side opposite to the first side. The display film layer is located on the pixel array, and an orthogonal projection of the display film layer on the substrate is spaced apart from an orthogonal projection of the circuit bridge structure on the substrate.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.

Abstract: A pixel array substrate including a substrate, a plurality of pixel structures and a scan device is provided. The pixel structures are arranged on the substrate along a first direction. Each pixel structure includes a data line, an active device and a pixel electrode. The active device has a semiconductor pattern, a source electrode and a drain electrode. The source electrode and the drain electrode are electrically connected to the data line and the pixel electrode respectively. The scan device includes a first and a second scan line. The first and the second scan line extend in the first direction and are electrically connected to each other. The active devices of the pixel structures are electrically connected to the first and the second scan line. The first and the second scan line respectively overlap two different regions of the semiconductor pattern of each active device.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Abstract: A pixel array substrate including a substrate, a plurality of pixel structures and a scan device is provided. The pixel structures are arranged on the substrate along a first direction. Each pixel structure includes a data line, an active device and a pixel electrode. The active device has a semiconductor pattern, a source electrode and a drain electrode. The source electrode and the drain electrode are electrically connected to the data line and the pixel electrode respectively. The scan device includes a first and a second scan line. The first and the second scan line extend in the first direction and are electrically connected to each other. The active devices of the pixel structures are electrically connected to the first and the second scan line. The first and the second scan line respectively overlap two different regions of the semiconductor pattern of each active device.

Abstract: An antenna performance evaluation method is disclosed. The method includes the following steps: measuring plurality of throughput values of the to-be-tested antenna at the first angle under different average radiation signal-to-interference ratio (SIR). The average radiation SIR and throughput values are fitted to output the first fitted curve. The second throughput value is measured at a certain average radiation SIR of the second angle of the to-be-tested antenna. Calculating a difference value between the first throughput value and the second throughput value corresponding to the same average radiation SIR, and the difference value and the first fitting curve constitute the transition second fitting curve. Selecting different average radiation SIR is repeatedly, and measure the corresponding second throughput value, and the corresponding difference value is calculated to update the transition second fitting curve.

Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.

Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.

Abstract: A preparation method of tetraboronic acid compounds includes mixing aldehydes with amines and dissolving them in a solvent to obtain a first solution, stirring the first solution, adding carboxylic acid and isocyanide to obtain a second solution, heating the second solution to obtain a first product, extracting and purifying the first product to obtain tetraboronate ester compounds, and executing a deprotection reaction on the tetraboronate ester compounds under heating by microwave to obtain a second product. The second product contains tetraboronic acid compounds, and the tetraboronic acid compounds have the structure as shown in formula (I).

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

Abstract: A device substrate including a substrate, first fan-out lines, second fan-out lines, third fan-out lines, touch electrode lines, and active devices is provided. The substrate includes an active area and a peripheral area connected with the active area. The first fan-out lines, the second fan-out lines, and the third fan-out lines are disposed on the peripheral area. Each of the second fan-out lines is overlapped with one corresponding first fan-out line. The second fan-out lines and the first fan-out lines belong to different conductive layers. Each of the third fan-out lines is disposed between two corresponding first fan-out lines. The third fan-out lines and the first fan-out lines belong to the same conductive layer. The touch electrode lines are electrically connected with the third fan-out lines. The active devices are disposed on the active area and electrically connected with the first fan-out lines and the second fan-out lines.

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.