Patents by Inventor Yi-Wei Chen

Yi-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10368431
    Abstract: According to some aspects of the present disclosure, cooling assemblies for electronic devices are disclosed. Example cooling assemblies include a circuit board having a first surface and a second surface opposite the first surface, a first set of electronic devices, a second set of electronic devices, and a third set of electronic devices. Each set includes at least two electronic devices electrically coupled in parallel and disposed on the first surface of the circuit board. At least one of the electronic devices of the first set is adjacent one of the electronic devices of the second set and is adjacent one of the electronic devices of the third set. The cooling assembly further includes a heat sink disposed on the second surface of the circuit board. The heat sink is in thermal contact with the first set, the second set, and the third set of electronic devices.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: July 30, 2019
    Assignee: Astec International Limited
    Inventors: Yu-wei Chen, Yi-kai Lan, Shih-chien Chou
  • Publication number: 20190229012
    Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsan-Chun WANG, De-Wei YU, Ziwei FANG, Yi-Fan CHEN
  • Patent number: 10355612
    Abstract: A flyback power converter circuit converting an input voltage to an output voltage includes a transformer, a power switch, a synchronous rectifier (SR) switch, and a secondary side control circuit. The secondary side control circuit controls the SR switch to be ON when the power switch is OFF. The secondary side control circuit includes a driving switch for controlling the SR switch, a synchronous control circuit powered by a voltage related to the output voltage, which controls the driving switch to operate the SR switch, and a clamping circuit including a clamping switch and a clamping switch control circuit. The clamping switch control circuit controls the clamping switch according to a current inflow terminal voltage of the clamping switch and/or the voltage related to the output voltage, such that, during a secondary side power-on period, an equivalent impedance of the current inflow terminal of the clamping switch is smaller than a predetermined clamping impedance.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: July 16, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chien-Fu Tang, Su-Yuan Lin, Yi-Wei Lee, Isaac Y. Chen
  • Publication number: 20190212185
    Abstract: A split detection device includes: a detection unit, which includes a detection casing and a sensor that is mounted inside the detection casing; a processing unit, which includes a processing casing and a processor that is mounted inside the processing casing; a connection unit, which is electrically connected between the sensor of the detection unit and the processor of the processing unit; and a transmission unit, which is electrically connected between the processor of the processing unit and an external device. By setting up the sensor and the processor inside different casings to be separate from each other, influence of the processor on the sensor can be reduced to thereby improve accuracy of detection.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Inventors: Wang-Chih Chen, Yih-Chyun Hwang, Szu-Wei Yu, Min-Hsiu Wu, Yi-Jun Feng
  • Publication number: 20190212790
    Abstract: An operation method of an electronic system includes the following steps. When a first communication module of the electronic device receives a call signal, a controller of an electronic device detects whether an expansion device is electrically connected to the electronic device. Based on a result of the controller detecting whether the expansion device is electrically connected to the electronic device, it is determined whether the electronic system performs sound amplification with a first speaker of the electronic device or performs playing with a second speaker of the expansion device.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 11, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: I-Lung Chen, Yi-Hsuan Wu, Wang-Hung Yeh, Yi-Chang Wu, Yu-Fan Chuang, Yu-Wei Lai
  • Publication number: 20190215393
    Abstract: A communication device includes a first body, a second body, a first audio module, and a second audio module. The second body is rotatably connected to the first body. The first audio module is disposed on the first body. The second audio module is at least partially disposed on the first body. When the second body rotates relatively to the first body to be in a first state to switch the communication device to be in a first operation mode, at least a portion of the first audio module is turned on, and the second audio module is turned off. When the second body rotates relatively to the first body to be in a second state to switch the communication device to be in a second operation mode, the first audio module is turned off, and the second audio module is turned on.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 11, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ching-Hua Li, Li-Fang Chen, Chen-Hsien Cheng, Yi-Chang Wu, Po-Yueh Lan, Yu-Wei Lai, Kun-Chang Chen, Yi-Chun Lin
  • Publication number: 20190214714
    Abstract: An antenna structure includes a housing, a feed portion, a ground portion, a first radiator, and a second radiator. The housing includes a first radiating portion and a second radiating portion. The first radiator and the second radiator are both positioned in the housing. When the feed portion feeds current, the current flows through the first radiating portion and is grounded through the ground portion to activate a first operating mode. When the feed portion feeds current, the current is further coupled to the first radiator through the first radiating portion, and the first radiator activates a second operating mode. When the second radiator feeds current, the second radiator activates a third operating mode. When the second radiator feeds current, the current is further coupled to the second radiating portion through the second radiator, and the second radiating portion activates a fourth operating mode.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 11, 2019
    Inventors: CHANG-JE CHEN, SHU-WEI JHANG, TUN-YUAN TSOU, YI-TE CHOU, YUNG-CHIN CHEN, CHANG-CHING HUANG
  • Publication number: 20190210594
    Abstract: A navigation system includes: a control unit configured to: receive a parking facility request for an autonomous vehicle operation of a user vehicle in a vehicle parking facility; retrieve a parking facility map for the vehicle parking facility, including facility information, for the vehicle parking facility, wherein the facility information includes intersection nodes; and generate a facility traversal route for the autonomous vehicle operation of the user vehicle through the vehicle parking facility based on the intersection nodes and the parking facility request.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 11, 2019
    Inventors: Alexander G. Glebov, Manuj Shinkar, Ninad Pradeep Lanke, Sarvesh Bansilal Devi, Kok Wei Koh, Po-Wen Chen, HaiPing Jin, Yi-Chung Chao
  • Patent number: 10347741
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes reflowing the conformal film. The method includes forming a cap layer on the reflowed film. The method includes depositing a crystalline film on the cap layer. The method includes crystallizing the reflowed film and the cap layer after depositing the crystalline film.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Ju Liang, De-Wei Yu, Yi-Cheng Li, Chien-Hao Chen
  • Patent number: 10340357
    Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
  • Patent number: 10340268
    Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
  • Patent number: 10332741
    Abstract: A method for post chemical mechanical polishing clean is provided in the present invention, which include the steps of providing a substrate, performing a chemical mechanical polishing process, and performing a plurality of cleaning processes sequentially substrate using solutions of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) with different ratios and at different temperatures.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Yu-Ren Wang
  • Patent number: 10331002
    Abstract: A pixel array substrate including a plurality of pixel units disposed on a substrate is provided. Each of the pixel units includes a scan line, a data line and an active element. The active element includes a semiconductor layer, a gate, a source electrode and a drain electrode. The semiconductor layer has a channel region, a source region, a drain region, a first connection region and a second connection region. The first connection region is connected between the channel region and the source region. The second connection region is connected between the channel region and the drain region. A normal projection of the first connection region on the substrate and a normal projection of the second connection region on the substrate are respectively located at two opposite sides of a normal projection of the data line on the substrate.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 25, 2019
    Assignee: Au Optronics Corporation
    Inventors: Hsiu-Chun Hsieh, Yi-Wei Chen
  • Patent number: 10324345
    Abstract: A display device and a display substrate are provided. The display device includes a first substrate, having a surface; a gate line disposed on the substrate, wherein the gate line substantially extends along a first direction; a first data line and a drain electrode disposed on the substrate, and the data line intersecting with the gate line. In particular, a first opening projects onto the surface to form a first projection pattern, wherein the first projection pattern includes a first portion, and wherein the first portion is disposed between projections of the at least two finger portions onto the surface and outside a projection of the connecting portion onto the surface.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: June 18, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Hung-Kun Chen, Yi-Chin Lee, Hong-Kang Chang, Yi-Chien Kao, Jui-Ching Chu, Li-Wei Sung, Hui-Min Huang
  • Patent number: 10312242
    Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 4, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chieh Chen, Pin-Hong Chen, Chih-Chieh Tsai, Chia-Chen Wu, Yi-An Huang, Kai-Jiun Chang, Tsun-Min Cheng, Yi-Wei Chen
  • Publication number: 20190161711
    Abstract: A semiconductor cleaning solution for cleaning a surface of a semiconductor device, and a method of use and a method of manufacture of the cleaning solution are disclosed. In an embodiment, a material is polished away from a first surface of the semiconductor device and the first surface is cleaned with the cleaning solution. The cleaning solution may include a host having at least one ring. The host may have a hydrophilic exterior and a hydrophobic interior.
    Type: Application
    Filed: October 5, 2018
    Publication date: May 30, 2019
    Inventors: Pinlei Edmund Chu, Chun-Wei Hsu, Ling-Fu Nieh, Chi-Jen Liu, Liang-Guang Chen, Yi-Sheng Lin
  • Publication number: 20190165177
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Application
    Filed: October 31, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Chih-Ming LAI, Ching-Wei TSAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kuo-Cheng CHING, Ru-Gun LIU, Wei-Hao WU, Yi-Hsiung LIN, Chia-Hao CHANG, Lei-Chun CHOU
  • Publication number: 20190165133
    Abstract: In some embodiments, a method is provided. Dummy gate stacks are formed over a semiconductor substrate. An interlayer dielectric (ILD) layer is formed over the dummy gate stacks. A first portion of the ILD layer over top surfaces of the dummy gate stacks is removed, such that a second portion of the ILD layer remains between the dummy gate stacks. The dummy gate stacks are replaced with metal gate stacks. Neutral NF3 radicals into the water are applied to etch the ILD layer.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 30, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Ruei JHAN, Yi-Lun CHEN, Fang-Wei LEE, Han-Yu LIN, Li-Te LIN, Pinyen LIN
  • Publication number: 20190164816
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a second layer. The method includes forming a first recess and a second recess in the first layer. The first recess is narrower than the second recess. The method includes forming a first covering layer in the first recess and the second recess. The first covering layer in the first recess is thinner than the first covering layer in the second recess. The method includes removing the first covering layer in the first recess and the first covering layer covering the first bottom surface to form a first opening in the first covering layer in the second recess. The method includes removing the first portion and the second portion through the first recess and the first opening.
    Type: Application
    Filed: August 17, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Xi-Zong CHEN, Chih-Hsuan LIN, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU
  • Publication number: 20190152214
    Abstract: A gravure offset printing apparatus includes two clamps, a printing roller and a driving device. The two clamps are applicable to clamp individually two opposing ends of a blanket. The printing roller having an axial direction parallel to a first direction is disposed between the two clamps. The blanket wraps part of a radial periphery of the printing roller. The driving device is to drive the two clamps to undergo reverse motions so as to displace the blanket, and the blanket further rotates the printing roller. A gravure module, disposed on a platform of the gravure offset printing apparatus, has a groove for containing an offset ink. While the two clamps pull the blanket to undergo the reverse motions, a surface of the blanket contacts the gravure module so as to adhere the offset ink on the surface of the blanket.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 23, 2019
    Inventors: Kai-Jiun Wang, Chih-Ming Chen, Yu-Ming Wang, Yi-Wei Lin