Patents by Inventor Yi Yang

Yi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149436
    Abstract: A method for manufacturing an interconnect structure includes: forming sacrificial portions and electrically conductive portions on a base structure such that the sacrificial portions are disposed to alternate with the electrically conductive portions in a first direction, and such that each of the sacrificial portions and the electrically conductive portions is elongated in a second direction transverse to the first direction; forming blocking portions respectively on the sacrificial portions; forming a sacrificial layer to cover the electrically conductive portions and the blocking portions; forming an electrically conductive via which extends through the sacrificial layer so as to permit the electrically conductive via to be electrically connected to one of the electrically conductive portions; after forming the electrically conductive via, performing a removal process to remove the sacrificial layer, the blocking portions and the sacrificial portions so as to form a cavity; and forming a dielectric portio
    Type: Application
    Filed: November 6, 2023
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gary LIU, Ting-Ya LO, Shao-Kuan LEE, Zi-Yi YANG, Chi-Lin TENG, Kuang-Wei YANG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Ming-Han LEE, Shau-Lin SHUE
  • Publication number: 20250140696
    Abstract: An interconnection structure includes a first dielectric layer, a second dielectric layer, a first conductive feature, and a second conductive feature. The second dielectric layer is disposed on one side of the first dielectric layer. The first conductive feature is embedded in the first dielectric layer or the second dielectric layer, the second conductive feature is embedded in the first dielectric layer or the second dielectric layer, wherein the first The conductive feature includes a first conductive material, the second conductive feature includes a second conductive material and a barrier layer, the first conductive material is different from the second conductive material. The first conductive material does not contain copper, and the second conductive material contains copper.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Tang HUNG, Tsu-Chun KUO, Shin-Yi YANG
  • Publication number: 20250143188
    Abstract: A method includes providing a first electrode, forming a stack of magnetic tunneling junction (MTJ) layers on the first electrode, forming a second electrode on the stack of MTJ layers, and forming a hybrid hard mask on the second electrode. The hybrid hard mask includes a first material layer, a second material layer, and a third material layer. The method also includes patterning the third material layer and the second material layer, patterning the first material layer while using the patterned third material layer and the patterned second material layer as a first mask, patterning the second electrode while using the patterned first material layer as a second mask, and etching the stack of MTJ layers and the first electrode using the patterned second electrode as a third mask. After the etching the stack of MTJ layers and the first electrode, the hybrid hard mask is completely removed.
    Type: Application
    Filed: December 30, 2024
    Publication date: May 1, 2025
    Inventors: Yi Yang, Yu-Jen Wang
  • Patent number: 12289702
    Abstract: An electronic device according to various embodiments of the present disclosure comprises: at least one wireless communication module; and a processor, wherein the processor can control the wireless communication module to respectively receive a plurality of pieces of data from a plurality of external electronic devices, identify a time when each of the plurality of pieces of data has been received, and, when location information regarding the plurality of external electronic devices is included in the plurality of pieces of data, calculate the location of the electronic device by using a time difference in reception of the plurality of pieces of data and the location information regarding the plurality of external electronic devices. Various other embodiments are also possible.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: April 29, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yi Yang, Moonseok Kang, Jonghoon Jang, Hyunchul Kim, Sejong Yoon, Sehwan Choi, Sukgi Hong
  • Publication number: 20250129164
    Abstract: This disclosure relates to anti-PD-1 (Programmed Cell Death Protein 1) antibodies, antigen-binding fragments, and the uses thereof.
    Type: Application
    Filed: November 14, 2024
    Publication date: April 24, 2025
    Inventors: Yi Yang, Chunyan Dong, Fang Yang, Chengyuan Lu, Yuelei Shen, Jian Ni, Yanan Guo, Yunyun Chen, Jingshu Xie
  • Publication number: 20250133967
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Application
    Filed: December 24, 2024
    Publication date: April 24, 2025
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20250132200
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes the following steps. A trench is formed in a first interlayer dielectric (ILD) layer. A metal conductor with metal dopants is filled in the trench. Planarization is performed on the metal conductor with the metal dopants. A thermal treatment, a photo treatment or a bias-assist treatment is performed on the metal conductor with the metal dopants to form a self-forming metal capping layer on a first metal layer. An etching stop bi-layer structure is formed on the first interlayer dielectric layer and the self-forming metal capping layer. A via, a second interlayer dielectric (ILD) layer and a second metal layer are formed on the etching stop bi-layer structure. The via is embedded in the second interlayer dielectric layer and the via is disposed between the first metal layer and the second metal layer.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Lung CHUNG, Shin-Yi YANG
  • Patent number: 12280070
    Abstract: A drug for the prevention or treatment of sepsis is provided. The drug comprises an exosome containing a circRNA MOTOR, and a nucleotide sequence corresponding to the circRNA MOTOR is shown in SEQ ID NO: 1.
    Type: Grant
    Filed: November 21, 2024
    Date of Patent: April 22, 2025
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Wei Huang, Haibo Qiu, Ke Fang, Jianfeng Xie, Ling Liu, Yi Yang, Ran Yang
  • Publication number: 20250123711
    Abstract: A circuit, for a touch panel, comprises a plurality of touch signal processing circuits, coupled to a plurality of sensors of the touch panel to receive a plurality of touch signals, wherein when a first sensor within the plurality of sensors is touched, the first sensor generates a first touch signal of the plurality of touch signals; and a controller, coupled to the plurality of touch signal processing circuits, configured to adjust the first touch signal according to the plurality of touch signals except the first touch signal.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 17, 2025
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Yaw-Guang Chang, Ren-Yuan Huang, Yi-Yang Tsai, Hao-Cheng Tsai
  • Publication number: 20250123855
    Abstract: A microservice migration method is applied to a cloud platform configured to manage an instance that provides a microservice, and includes: obtaining stored first microservice configuration information of a target microservice from a first configuration center running on a first instance; generating second microservice configuration information of a migrated target microservice based on the first microservice configuration information; and sending the second microservice configuration information to a second configuration center running on a second instance, where the second configuration center is configured to store configuration information of the migrated target microservice. In this way, during microservice migration, microservice configuration information may be obtained from an original configuration center, and then based on the microservice configuration information, microservice configuration information adapted to a new configuration center is obtained.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Applicant: Huawei Cloud Computing Technologies Co., Ltd.
    Inventors: Yi Yang, Shengsheng Zhou, Jianwen Luo
  • Publication number: 20250122292
    Abstract: This disclosure relates to antigen-binding protein constructs (e.g., bispecific antibodies, antigen-binding fragments thereof, or ADCs), wherein the antigen-binding protein constructs specifically bind to two different antigens (e.g., EGFR and MET).
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Inventors: Yanfei HAN, Chengzhang SHANG, Baihong LIU, Yi YANG, Yuelei SHEN
  • Publication number: 20250125251
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, strained layers, source/drain contact patterns, a gate contact via, and source/drain contact vias. The gate structure is disposed over the semiconductor substrate. The strained layers are disposed aside the gate structure. The source/drain contact patterns are disposed on and electrically connected to the strained layers. Top surfaces of the source/drain contact patterns are coplanar with a top surface of the gate structure. The gate contact via is disposed on and electrically connected to the gate structure. The source/drain contact vias are disposed on and electrically connected to the source/drain contact patterns.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ling Su, Chia-Wei Su, Tsu-Chun Kuo, Wei-Hao Liao, Hsin-Ping Chen, Yung-Hsu Wu, Ming-Han Lee, Shin-Yi Yang, Chih Wei LU, Hsi-Wen Tien, Meng-Pei Lu
  • Patent number: 12277709
    Abstract: A wound-size measuring method for use in a portable electronic device is provided. The method includes the following steps: obtaining an input image via a camera device of the portable electronic device; using a CNN (convolutional neural network) model to recognize the input image, and selecting a part of the input image with the highest probability of containing a wound as an output wound image; and calculating an actual height and an actual width of the output wound image according to a lens-focal-length parameter reported by an operating system running on the portable electronic device, a plurality of reference calibration parameters corresponding to a pitch angle of the portable electronic device, and a pixel-height ratio and a pixel-width ratio of the output wound image.
    Type: Grant
    Filed: November 25, 2021
    Date of Patent: April 15, 2025
    Assignee: WISTRON CORP.
    Inventors: Wen Hsin Hu, Ji-Yi Yang, Zhe-Yu Lin, Hui Chi Hsieh, Yin Chi Lin, Chi Lun Huang
  • Publication number: 20250115668
    Abstract: An antigen-binding protein constructs (e.g., bispecific antibodies or antigen-binding fragments thereof), wherein the antigen-binding protein constructs specifically bind to two different antigens (e.g., CTLA4 and OX40).
    Type: Application
    Filed: January 30, 2023
    Publication date: April 10, 2025
    Inventors: Baihong Liu, Yanfei Han, Yan Huang, Xin Ji, Yi Yang, Yuelei Shen
  • Publication number: 20250115419
    Abstract: A shipping container connector includes a first latch unit, a second latch unit and a pulling rope unit. The first latch unit has a first body member, a first latch portion. The first body member has two side walls cooperatively defining a mounting space. One of the side walls has a threading hole. The second latch unit is disposed in the mounting space, and includes a second body member, and a spring member. The pulling rope unit extends through the threading hole, and has an end fixed to the second latch unit, and an opposite end disposed outside of the threading hole. When the pulling rope unit is pulled, the second latch unit is driven to move relative to the first latch unit from a locked position to a released position, where the spring member accumulates a biasing force for biasing the second latch unit towards the locked position.
    Type: Application
    Filed: February 19, 2024
    Publication date: April 10, 2025
    Inventors: Jung-Kuang HSIEH, Pei-Yi YANG
  • Patent number: 12270482
    Abstract: A valve includes a valve body, a valve plate, and an actuation mechanism, wherein the valve body includes two plates parallel to each other and symmetrical and on which medium access holes are correspondingly opened; sealing rings a are symmetrically provided on inner surfaces of the two plates, and the medium access holes on the two plates are completely located within circumferentially closed holes of the sealing rings a; the valve plate has a smooth surface and is tightly sandwiched between the sealing rings a when the valve is closed; a fastening structure is installed on the two plates of the valve body and clamps the two plates and/or the sealing rings a around radial peripheries of the sealing rings a; and at least a part of the fastening structure can adjust its clamping degree in a direction perpendicular to a surface of the valve body.
    Type: Grant
    Filed: May 1, 2021
    Date of Patent: April 8, 2025
    Assignee: DALIAN CONSERVATION SCIENCE &TECHNOLOGY CO., LTD.
    Inventors: Jiaxian Wang, Nianlei Liu, Yi Yang
  • Patent number: 12272623
    Abstract: Embodiments of the present disclosure provide a stacking edge interconnect chiplet. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first integrated circuit die comprising a first device layer having a first side and a second side opposite the first side, a first interconnect structure disposed on the first side of the first device layer, and a second interconnect structure disposed on the second side of the first device layer. The semiconductor device also includes a power line extending through the first device layer and in contact with the first interconnect structure and the second interconnect structure, and a second integrated circuit die disposed over the first integrated circuit die, the second integrated circuit die comprising a third interconnect structure in contact with the second interconnect structure of the first integrated circuit die.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 12273140
    Abstract: An electronic device according to an embodiment of the disclosure may receive an advertising frame transmitted by an external electronic device through the communication circuit through ultra-wideband (UWB) communication, may receive at least one frame among the advertising frames in a first decision period, may determine whether the number of times an angle based on the at least one frame received in the first decision period is within a specified angle range satisfies a specified condition, and may determine whether the electronic device points to the external electronic device according to whether the specified condition is satisfied.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: April 8, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunchul Kim, Moonseok Kang, Yi Yang, Jonghoon Jang
  • Patent number: 12270932
    Abstract: An electronic device includes an ultra-wide band (UWB) circuit, and at least one processor comprising a controller of UWB circuit. The at least one processor is configured to transmit, through UWB circuit operating in a first mode, a first signal for a first field in a first frame, transmit, through UWB circuit operating in the first mode, a second signal including designated information for a second field in the first frame, receive, through UWB circuit operating in the first mode, a first reflected signal related to the first signal and a second reflected signal related to the second signal, respectively, caused by an external object, according to a state of the designated information identified from the second reflected signal, obtain information on the external object based on the first reflected signal or transmit a second frame through UWB circuit operating in a second mode.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 8, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunchul Kim, Yi Yang, Moonseok Kang, Jiho Shin
  • Publication number: 20250112089
    Abstract: A structure including a conductive region, a dielectric region, and a capping layer is provided. The conductive region is disposed on or embedded in the dielectric region. The capping layer is disposed on the conductive region. A material of the capping layer includes a 2D material.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Wei Li, Shin-Yi Yang