Abstract: A layout structure of double-sided flexible circuit board includes a flexible substrate having a first surface and a second surface, a first circuit layer and a second circuit layer. An inner bonding region is defined on the first surface and an inner supporting region is defined on the second surface according to the inner bonding region. The first circuit layer is located on the first surface and includes first conductive lines which each includes an inner lead located on the inner bonding region. The second circuit layer is located on the second surface and includes second conductive lines which each includes an inner supporting segment located on the inner supporting region. A width difference between any two of the inner supporting segment of the second conductive lines is less than 8 ?m.

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Abstract: The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a substrate having a memory cell region and a peripheral region, wherein the memory cell region has at least one first shallow trench isolation and the peripheral region has at least one second shallow trench isolation; a plurality of gates in the first shallow trench isolation; a first semiconductor layer in the peripheral region; a first insulating layer covering the substrate in the memory cell region; a crystalline overlayer in the memory cell region and a doped portion of the substrate below the crystalline overlayer; and a second semiconductor layer on a portion of the first insulating layer, wherein a top surface of the first semiconductor layer and a top surface of the second semiconductor layer are coplanar.

Abstract: The disclosure provides an active peptide with an anti-lipid oxidation function and a preparation method and application thereof and belongs to the technical field of plant-derived biologically active peptides. In the disclosure, oil processing by-products, namely oil crops after oil extraction, are used as the raw materials, and the raw materials are subjected to the steps of protein extraction, infrared pretreatment, proteolysis, freeze-drying, lipophilic part extraction, vacuum concentration and drying and the like to prepare an anti-lipid oxidation peptide having the functional characteristics of scavenging DPPH free radicals, chelating metal ions, inhibiting lipid peroxidation, prolonging vegetable oil oxidation induction time, improving emulsion stability and the like.

Abstract: A backpack tool, a backpack blower and a control handle assembly are provided by the present invention. The backpack tool includes a battery pack for providing electrical energy, a power assembly electrically connected with the battery pack to convert the electrical energy provided by the battery pack into mechanical energy, and a backpack assembly carried on the human back to support the battery pack and the power assembly. Both the battery pack and the power assembly can be carried on the human back using the backpack assembly, so that the weight carried by the arms of the worker can be reduced. The battery pack serves as a power source that reduces the noise and vibration caused by the backpack tool during operation as compared with a gasoline powered backpack tool.

Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.

Abstract: A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.

Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.

Abstract: A method of generating an integrated circuit includes: placing a plurality of electronic components on a layout floor plan to generate a placing layout of the integrated circuit; forming a clock tree upon the placing layout to generate a synthesis layout of the integrated circuit; routing the synthesis layout to generate a routed layout of the integrated circuit; performing a DRC process upon the routed layout to obtain a layout region with a systematic DRC violation; generating a plurality of prediction gains of the layout region according to a plurality of placement recipes respectively; and generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in the plurality of placement recipes.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

Abstract: A topical formulation comprising (a) a therapeutically effective amount of tofacitinib; (b) at least one solvent; and (c) optionally one or more other pharmaceutically acceptable excipients is provided. Also provided is a method for treating and/or preventing autoimmune diseases in a subject administering said topical formulation.

Abstract: Systems and methods are disclosed. A controller includes one or more processors; and one or more non-transitory memory modules storing machine-readable instructions that, when executed, cause the one or more processors to obtain environment data associated with a vehicle; obtain trajectory data associated with the vehicle; and identify one or more edge servers associated with the trajectory data. The machine-readable instructions, when executed, cause the one or more processors to obtain edge server state information of the one or more edge servers; select a first set of the environment data to transmit to a first edge server of the one or more edge servers based on the edge server state information of the one or more edge servers; and generate an instruction signal causing the vehicle to transmit the first set of the environment data to the first edge server of the one or more edge servers.

Abstract: A finFET device and methods of forming a finFET device are provided. The device includes a fin and a capping layer over the fin. The device also includes a gate stack over the fin, the gate stack including a gate electrode and a gate dielectric. The gate dielectric extends along sidewalls of the capping layer. The device further includes a gate spacer adjacent to sidewalls of the gate electrode, the capping layer being interposed between the gate spacer and the fin.

Abstract: A direction determination system and a direction determination method are provided. The direction determination system includes a display screen, at least one image capturing device and a processing device. The image capturing device is configured to capture image data including a plurality of users. The processing device is coupled to the display screen and the image capturing device to receive the image data, and detects a plurality of characteristics of the plurality of users according to the image data. The processing device performs corresponding pairing on the characteristics to obtain a characteristic group of each of the users. The processing device determines a pointing direction of each of the users toward the display screen according to at least two characteristics of the characteristic group of each of the users.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: A method includes providing a structure having a substrate and a fin protruding from the substrate, forming a gate stack layer over the fin, and patterning the gate stack layer in forming a gate stack. The patterning of the gate stack layer simultaneously forms a passivation layer on sidewall surfaces of the gate stack. The method also includes removing a bottom portion of the passivation layer, thereby exposing a bottom portion of the gate stack, while a top portion of the passivation layer remains. The method further includes laterally etching the bottom portion of the gate stack, thereby shrinking a width of the bottom portion of the gate stack.

Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.