Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.

Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A second neural network for video stabilization is trained to generate stabilized HDR images in a time-dependent manner.

Abstract: A method of generating an integrated circuit includes providing a placing layout of the integrated circuit; generating a routed layout of the integrated circuit, the routed layout includes a layout region with a systematic design rule check (DRC) violation; generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in a plurality of placement recipes; extracting features of the placing layout to obtain an extracted data; extracting features of the layout region with the systematic DRC violation to obtain an extracted routing data; performing a training process upon the extracted data and the extracted routing data to generate a plurality of aggregated-cluster models; and selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models.

Abstract: A method for forming semiconductor devices includes providing a substrate with a conductive pad formed thereon; forming a transparent structure over the substrate, wherein the transparent structure includes a plurality of collimating pillars adjacent to the conductive pad; forming a light-shielding structure over the plurality of collimating pillars and the conductive pad; performing a cutting process to remove one or more materials directly above the conductive pad, while leaving remaining material to cover the conductive pad, wherein the material includes a portion of the light-shielding structure; and performing an etching process to remove the remaining material to expose the conductive pad.

Abstract: A layout structure of double-sided flexible circuit board includes a flexible substrate having a first surface and a second surface, a first circuit layer and a second circuit layer. An inner bonding region is defined on the first surface and an inner supporting region is defined on the second surface according to the inner bonding region. The first circuit layer is located on the first surface and includes first conductive lines which each includes an inner lead located on the inner bonding region. The second circuit layer is located on the second surface and includes second conductive lines which each includes an inner supporting segment located on the inner supporting region. A width difference between any two of the inner supporting segment of the second conductive lines is less than 8 ?m.

Abstract: A flexible circuit board includes a flexible light-permeable carrier, a circuit layer, a mark and a stiffener. The circuit layer and the mark are located on a top surface of the flexible light-permeable carrier. A predetermined area and a stiffener mounting area corresponding to each other are defined on the top surface and a bottom surface of the flexible light-permeable carrier, respectively. The mark is opaque to create a shadow mark having a longitudinal reference side and a lateral reference side on the bottom surface. The stiffener is adhered to the stiffener mounting area defined on the bottom surface by aligning with the longitudinal reference side and the lateral reference side of the shadow mark.

Abstract: The present application discloses a method for fabricating a semiconductor device with a self-aligned landing pad. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer. The landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.

Abstract: A method for fabricating a semiconductor device includes providing a structure having two fins over a substrate, lower portions of the fins being separated by an isolation structure, a dummy gate structure over the fins, and source/drain features over the fins on both sides of the dummy gate structure; forming a trench in the dummy gate structure between the two fins, where forming the trench removes a portion of the isolation structure; forming a dielectric layer in the trench, where a bottom surface of the dielectric layer extends below a top surface of the isolation structure; and replacing the dummy gate structure with one high-k metal gate structure formed over one of the fins and another high-k metal gate structure formed over the other of the fins.

Abstract: An optical integration device includes a first circuit layer comprising a first surface adjacent a first diffractive layer, the first diffractive layer arranged on a side of the first circuit layer along a first direction, and a first connecting pad electrically connected with the first circuit layer through a first conductive member. The optical integration device includes a side surface extending along the first direction. The side surface defines a first concavity extending through the first diffractive layer along the first direction. The first connecting pad includes a first mounting member connected with the side surface, and a first convex member extending from the first mounting member and received in the first concavity. The first conductive member includes a first conductive part arranged between the side surface and the first mounting member, and a second conductive part arranged between the first surface and the first convex member.

Abstract: A system and method for facilitating physical therapy that may include a wearable display, wearable sensors disposed at varying positions on a user, a processor comprising executable instructions configured to provide a virtual reality environment, virtual characters, and therapeutic activities on the wearable display, wherein the virtual characters interact with the user to provide at least form feedback and positive reinforcement. A new instance of the virtual reality environment, with identifiable differences, may be generated in response to a measured completion or partial completion of a therapeutic activity. Changes in the virtual reality environment may offer users continued indications of progression throughout the duration of a physical therapy program.

Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a dielectric layer, a contact plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The dielectric layer is positioned over the gate structure and the source/drain structure. The contact plug is positioned passing through the dielectric layer. The contact plug includes a first metal compound including one of group III elements, group IV elements, group V elements or a combination thereof.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

Abstract: The present application discloses a semiconductor device with a self-aligned landing pad and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a dielectric layer disposed over the substrate, a plug disposed in the dielectric layer, and a self-aligned landing pad disposed over the dielectric layer. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer in a self-aligned manner. The self-aligned landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.