Abstract: A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.

Abstract: Systems and methods described herein relate to managing an automotive edge computing environment. One embodiment receives current status information from one or more edge servers; receives and queues requested computing tasks from one or more connected vehicles; selects, as an optimization trigger number N, a largest number of requested computing tasks for which an optimization process can be completed within a time, per requested computing task, that is less than an average time gap between the requested computing tasks; performs the optimization process when a number of queued requested computing tasks exceeds the optimization trigger number N, wherein the optimization process produces an updated data transfer schedule and an updated data process schedule for N queued requested computing tasks; and transmits the updated data transfer schedule and the updated data process schedule to the one or more edge servers and the one or more connected vehicles.

Abstract: The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a tunneling insulating layer disposed over the substrate, a floating gate disposed over the tunnel oxide layer, a lateral oxidized intervention layer disposed over the floating gate, and a control gate disposed over the dielectric layer. The lateral oxidized intervention layer comprises a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion.

Abstract: An adjustable workpiece support system includes an adjustable support apparatus, an analysis support point module, a coordinate post-processing module and a control module. The adjustable support apparatus has a group of support devices for supporting a supported workpiece, the each support device being adjustable in height and angle. The analysis support point module is used to import a computer-aided design file of the supported workpiece, and analyze the computer-aided design file to obtain a group of support points of the supported workpiece. The coordinate post-processing module is configured to calculate the support coordinates of the each support device corresponding to the group of support points. The control module is configured to receive the support coordinates of the each support device, and adjust the height and angle of the each support device to support the supported workpiece, so that the amount of deformation of the supported workpiece is the minimum.

Abstract: Systems and methods described herein relate to managing an automotive edge computing environment. One embodiment receives current status information from one or more edge servers; receives and queues requested computing tasks from one or more connected vehicles; selects, as an optimization trigger number N, a largest number of requested computing tasks for which an optimization process can be completed within a time, per requested computing task, that is less than an average time gap between the requested computing tasks; performs the optimization process when a number of queued requested computing tasks exceeds the optimization trigger number N, wherein the optimization process produces an updated data transfer schedule and an updated data process schedule for N queued requested computing tasks; and transmits the updated data transfer schedule and the updated data process schedule to the one or more edge servers and the one or more connected vehicles.

Abstract: A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin.

Abstract: An electronic device for signal interference compensation is provided. The first signal line is electrically connected to the transmitter. The second signal line is electrically connected to the receiver and coupled with the first signal line. The electrode is electrically connected to the second signal line and measures a physiological signal. The processor is electrically connected to the transmitter and the receiver, and configured to: transmit, via the transmitter, an active signal to the first signal line; receive, via the receiver, a coupling signal corresponding to the active signal from the second signal line, and calculate a compensation value according to the coupling signal; and receive, via the receiver, an interfered signal corresponding to the physiological signal, and restore the physiological signal according to the compensation value and the interfered signal in response to the compensation value matching the interfered signal.

Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: A diaper outer cover includes a front lateral end (13) and a rear lateral end (19); a first longitudinal edge and a second longitudinal edge; and an adjustment system (400). The adjustment system has an adjustment strip (40) disposed in a leg gasketing system (52) or in a waist feature (50); and multiple engagement points (406). The adjustment system is selected from the group consisting of buckle mechanisms (420), snap mechanisms, lock and key mechanisms (426, 428), tying mechanisms (424), hook and loop mechanisms (405, 407), male and female mechanisms (412, 414) and combinations thereof.

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

Abstract: An outer cover includes a first lateral end, a second lateral end, and a length Lc extending in a longitudinal direction between the first and second lateral ends; and a first longitudinal edge and a second longitudinal edge. The outer cover also includes an opening. The opening has a maximum longitudinal length, Lo, that is at least 50% of the length of the outer cover, Lc; and the opening is adapted to receive an absorbent insert.

Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

Abstract: System, methods, and other embodiments described herein relate to improving execution of processing requests by an edge server. In one embodiment, a method includes predicting a number of computing requests from vehicles for execution by the edge server using a prediction solver for a time period that is forthcoming. The prediction solver may predict the number of computing requests using a prediction model selected in association with service constraints of the edge server and information from an additional server. The method also includes determining a request handling scheme using an optimization solver according to the number of computing requests, the service constraints of the edge server, and a service area of the edge server. The method also includes communicating the request handling scheme and a resource schedule to the edge server on a condition that a resources criteria are satisfied for the time period.

Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.

Abstract: A first semiconductor fin and a second semiconductor fin are disposed over a substrate. The second semiconductor fin and the first semiconductor fin are aligned substantially along a same line and spaced apart from each other. The first semiconductor fin has a first end portion, the second semiconductor fin has a second end portion, and an end sidewall of the first end portion and is spaced apart from an end sidewall of the second end portion. The gate structure extends substantially perpendicularly to the first semiconductor fin. When viewed from above, the gate structure overlaps with the first end portion of the first semiconductor fin. When viewed from above, the end sidewall of the first end portion of the first semiconductor fin facing the end sidewall of the second end portion of the second semiconductor fin has a re-entrant profile.

Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

Abstract: In accordance with some embodiments, a source/drain contact is formed by exposing a source/drain region through a first dielectric layer and a second dielectric layer. The second dielectric layer is recessed under the first dielectric layer, and a silicide region is formed on the source/drain region, wherein the silicide region has an expanded width.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.