Patents by Inventor Yin Chen

Yin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220140079
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.
    Type: Application
    Filed: January 17, 2022
    Publication date: May 5, 2022
    Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
  • Patent number: 11319569
    Abstract: The disclosure provides an active peptide with an anti-lipid oxidation function and a preparation method and application thereof and belongs to the technical field of plant-derived biologically active peptides. In the disclosure, oil processing by-products, namely oil crops after oil extraction, are used as the raw materials, and the raw materials are subjected to the steps of protein extraction, infrared pretreatment, proteolysis, freeze-drying, lipophilic part extraction, vacuum concentration and drying to prepare an anti-lipid oxidation peptide having the functional characteristics of scavenging DPPH free radicals, chelating metal ions, inhibiting lipid peroxidation, prolonging vegetable oil oxidation induction time, improving emulsion stability and the like.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: May 3, 2022
    Assignee: Jiangnan University
    Inventors: Yuanfa Liu, Zhaojun Zheng, Jiaxin Li, Yongjiang Xu, Yin Chen
  • Patent number: 11315964
    Abstract: An optical sensor includes pixels disposed in a substrate. A light collimating layer is disposed on the substrate and includes a transparent layer, a light-shielding layer, and transparent pillars. The transparent layer blanketly disposed on the substrate covers the pixels and the region between the pixels. The light-shielding layer is disposed on the transparent layer and between the transparent pillars. The transparent pillars penetrating through the light-shielding layer are correspondingly disposed on the pixels.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: April 26, 2022
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Hui Lee, Han-Liang Tseng, Jiunn-Liang Yu, Kwang-Ming Lin, Yin Chen, Si-Twan Chen, Hsueh-Jung Lin, Wen-Chih Lu, Ting-Jung Lu
  • Publication number: 20220122884
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 21, 2022
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Publication number: 20220123127
    Abstract: A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Inventor: TE-YIN CHEN
  • Patent number: 11309189
    Abstract: A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Chia-Yang Liao, Bo-Feng Young
  • Publication number: 20220116479
    Abstract: Systems and methods described herein relate to managing an automotive edge computing environment. One embodiment receives current status information from one or more edge servers; receives and queues requested computing tasks from one or more connected vehicles; selects, as an optimization trigger number N, a largest number of requested computing tasks for which an optimization process can be completed within a time, per requested computing task, that is less than an average time gap between the requested computing tasks; performs the optimization process when a number of queued requested computing tasks exceeds the optimization trigger number N, wherein the optimization process produces an updated data transfer schedule and an updated data process schedule for N queued requested computing tasks; and transmits the updated data transfer schedule and the updated data process schedule to the one or more edge servers and the one or more connected vehicles.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 14, 2022
    Inventors: Yin-Chen Liu, BaekGyu Kim
  • Patent number: 11298787
    Abstract: An adjustable workpiece support system includes an adjustable support apparatus, an analysis support point module, a coordinate post-processing module and a control module. The adjustable support apparatus has a group of support devices for supporting a supported workpiece, the each support device being adjustable in height and angle. The analysis support point module is used to import a computer-aided design file of the supported workpiece, and analyze the computer-aided design file to obtain a group of support points of the supported workpiece. The coordinate post-processing module is configured to calculate the support coordinates of the each support device corresponding to the group of support points. The control module is configured to receive the support coordinates of the each support device, and adjust the height and angle of the each support device to support the supported workpiece, so that the amount of deformation of the supported workpiece is the minimum.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: April 12, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Ting Chen, Chien-Chih Liao, Pei-Yin Chen, Bo-Jyun Jhang, Jen-Ji Wang
  • Patent number: 11302827
    Abstract: The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a tunneling insulating layer disposed over the substrate, a floating gate disposed over the tunnel oxide layer, a lateral oxidized intervention layer disposed over the floating gate, and a control gate disposed over the dielectric layer. The lateral oxidized intervention layer comprises a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: April 12, 2022
    Assignee: NANYA TECHNOLOGY CORP.
    Inventor: Te-Yin Chen
  • Patent number: 11296211
    Abstract: A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: April 5, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Te-Yin Chen
  • Patent number: 11297161
    Abstract: Systems and methods described herein relate to managing an automotive edge computing environment. One embodiment receives current status information from one or more edge servers; receives and queues requested computing tasks from one or more connected vehicles; selects, as an optimization trigger number N, a largest number of requested computing tasks for which an optimization process can be completed within a time, per requested computing task, that is less than an average time gap between the requested computing tasks; performs the optimization process when a number of queued requested computing tasks exceeds the optimization trigger number N, wherein the optimization process produces an updated data transfer schedule and an updated data process schedule for N queued requested computing tasks; and transmits the updated data transfer schedule and the updated data process schedule to the one or more edge servers and the one or more connected vehicles.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: April 5, 2022
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Yin-Chen Liu, BaekGyu Kim
  • Publication number: 20220102139
    Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.
    Type: Application
    Filed: June 21, 2021
    Publication date: March 31, 2022
    Inventors: Chih-Kai YANG, Yu-Tien SHEN, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
  • Publication number: 20220096019
    Abstract: An electronic device for signal interference compensation is provided. The first signal line is electrically connected to the transmitter. The second signal line is electrically connected to the receiver and coupled with the first signal line. The electrode is electrically connected to the second signal line and measures a physiological signal. The processor is electrically connected to the transmitter and the receiver, and configured to: transmit, via the transmitter, an active signal to the first signal line; receive, via the receiver, a coupling signal corresponding to the active signal from the second signal line, and calculate a compensation value according to the coupling signal; and receive, via the receiver, an interfered signal corresponding to the physiological signal, and restore the physiological signal according to the compensation value and the interfered signal in response to the compensation value matching the interfered signal.
    Type: Application
    Filed: January 8, 2021
    Publication date: March 31, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Cheng-Hung Yu, Shuen-Yu Yu, Heng-Yin Chen
  • Patent number: 11289417
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho
  • Publication number: 20220093758
    Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.
    Type: Application
    Filed: April 6, 2021
    Publication date: March 24, 2022
    Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220087882
    Abstract: A diaper outer cover includes a front lateral end (13) and a rear lateral end (19); a first longitudinal edge and a second longitudinal edge; and an adjustment system (400). The adjustment system has an adjustment strip (40) disposed in a leg gasketing system (52) or in a waist feature (50); and multiple engagement points (406). The adjustment system is selected from the group consisting of buckle mechanisms (420), snap mechanisms, lock and key mechanisms (426, 428), tying mechanisms (424), hook and loop mechanisms (405, 407), male and female mechanisms (412, 414) and combinations thereof.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 24, 2022
    Inventors: Donald Carroll ROE, Udo Friedel SCHOENBORN, Yin CHEN, Sara Lyn GIOVANNI, Tonya Mae Sheldon WEST, Gaƫlle Sandra WIZENBERG, Ana Cecilia MONTILLA RAMOS
  • Publication number: 20220087873
    Abstract: An outer cover includes a first lateral end, a second lateral end, and a length Lc extending in a longitudinal direction between the first and second lateral ends; and a first longitudinal edge and a second longitudinal edge. The outer cover also includes an opening. The opening has a maximum longitudinal length, Lo, that is at least 50% of the length of the outer cover, Lc; and the opening is adapted to receive an absorbent insert.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 24, 2022
    Inventors: Yin Chen, Sara Lynn Giovanni
  • Publication number: 20220085203
    Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Chang-Yin CHEN, Che-Cheng CHANG, Chih-Han LIN
  • Publication number: 20220087017
    Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.
    Type: Application
    Filed: July 20, 2021
    Publication date: March 17, 2022
    Inventors: Yin-Chen Lin, Ming-Hsiao Ke, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Publication number: 20220083391
    Abstract: System, methods, and other embodiments described herein relate to improving execution of processing requests by an edge server. In one embodiment, a method includes predicting a number of computing requests from vehicles for execution by the edge server using a prediction solver for a time period that is forthcoming. The prediction solver may predict the number of computing requests using a prediction model selected in association with service constraints of the edge server and information from an additional server. The method also includes determining a request handling scheme using an optimization solver according to the number of computing requests, the service constraints of the edge server, and a service area of the edge server. The method also includes communicating the request handling scheme and a resource schedule to the edge server on a condition that a resources criteria are satisfied for the time period.
    Type: Application
    Filed: September 11, 2020
    Publication date: March 17, 2022
    Inventors: Yin-Chen Liu, BaekGyu Kim