Ying Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
June 9, 2022
September 22, 2022
Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
Abstract: A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.
Abstract: The disclosure is directed to low molecular weight polyelectrolyte complex nanoparticles that can be used to deliver agents deep into hydrocarbon reservoirs. Methods of making and using said polyelectrolyte complex nanoparticles are also provided.
April 19, 2021
Date of Patent:
September 20, 2022
UNIVERSITY OF KANSAS, CONOCOPHILLIPS COMPANY
Stephen J Johnson, Cory Berkland, Ahmad Moradi-Araghi, Jenn-Tai Liang, Terry M. Christian, Riley B. Needham, Min Cheng, Ying-Ying Lin, Andrew B. Woodside
Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.
Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.
Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.
Abstract: Methods, compositions, kits and apparatuses that include a fluid, the fluid containing a ternary complex and Li+, wherein the ternary complex includes a primed template nucleic acid, a polymerase, and a nucleotide cognate for the next correct base for the primed template nucleic acid molecule. As an alternative or addition to Li+, the fluid can contain betaine or a metal ion that inhibits polymerase catalysis such as Ca2+. In addition to Li+, the fluid can contain polyethylenimine (PEI) with or without betaine.
January 4, 2022
September 15, 2022
Morassa Mohseni MIDDLETON, Mark C. WALLEN, Pinar IYIDOGAN, Michael James SCHMIDT, Brittany A. ROHRMAN, Ying Lin LIU, Fabian BLOCK, Arnold OLIPHANT
Abstract: A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.
Abstract: The present disclosure provides a method (100) in a network node advertising a Binding Segment Identifier, BSID. The method (100) includes: receiving (110) a first echo request packet containing a first target Forwarding Equivalence Class, FEC, stack including an FEC associated with the BSID; and transmitting (120), in response to a Time To Live, TTL, expiration associated with the first echo request packet, a first echo reply packet to an initiating network node initiating the first echo request packet, the first echo reply packet containing an indicator indicating that the FEC is to be replaced by a set of FECs.
Abstract: A system includes a non-transitory storage medium encoded with a set of instructions and a processor. The processor is configured to execute the set of instructions. The set of instructions is configured to cause the processor to: obtain, based on a netlist of a circuit, values each corresponding to one of transistors included in the circuit; compare the values with a threshold value; in response to a comparison, generate an adjusted netlist of the circuit by adding redundant transistors; and determine, based on the adjusted netlist, one of layout configurations for the circuit. The layout configurations include first cell rows each having a first row height and second cell rows each having a second row height different from the first row height.
Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.
Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.
Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
Abstract: The present disclosure provides a manufacturing method of a titanium dioxide solution and a titanium dioxide film. The manufacturing method of the titanium dioxide solution includes: mixing choline chloride, urea, boric acid, and titanium tetrachloride to form a first solution, wherein a molar concentration ratio of choline chloride to urea is 1:2, a molar concentration of titanium tetrachloride is 0.2 M to 0.4 M, and weight/volume of boric acid is 5 g/300 ml to 15 g/300 ml; and heating the first solution to form a second solution, wherein the second solution contains carbon/nitrogen doped titanium dioxide. In the manufacturing method of the present disclosure, the deep eutectic solution formed by choline chloride and urea may be used as a solvent, and may also be used as a carbon source and/or a nitrogen source. Therefore, titanium dioxide may be doped with carbon and/or nitrogen during the formation process.
Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
Abstract: A portable computing device including a central processing unit (CPU) and a controller is provided. The controller is coupled between the CPU, a graphics processing unit, and a battery module. The controller determines whether to adjust performance of the CPU and the graphics processing unit according to at least one of a battery capacity, a battery power, a battery current, a battery voltage, or a battery temperature of the battery module.
February 10, 2022
September 8, 2022
ASUSTeK COMPUTER INC.
Hao-Hsuan Lin, Yu-Hsiu Su, Chun-Nan Wang, Jia-Ying Wu, Chia-Sen Chang, Yu-Cheng Shen, Shih-Hsiang Kao
Abstract: The present disclosure provides a method for fabricating DRAM devices with cylinder-type stacked capacitors. By utilizing offsetting of a first lattice pattern on a second silicon nitride layer (i.e., a middle silicon nitride layer) and a second lattice pattern on a third silicon nitride layer (i.e., a top silicon nitride layer), a collapse or deformation phenomenon of bottom electrodes of stacked capacitors can be reduced or eliminated. The wobbling phenomenon of bottom electrodes of stacked capacitors can be significantly reduced.
Abstract: An automated calibration system for a workpiece coordinate frame of a robot includes a physical image sensor having a first image central axis, and a controller for controlling the physical image sensor adapted on a robot to rotate by an angle to set up a virtual image sensor having a second image central axis. The first and the second image central axes are intersected at an intersection point. The controller controls the robot to repeatedly move back and forth a characteristic point on the workpiece between these two axes until the characteristic point overlaps the intersection point. The controller records a calibration point including coordinates of joints of the robot, then the controller moves another characteristic point and repeats the foregoing movement to generate several other calibration points. According to the calibration points, the controller calculates relative coordinates of a virtual tool center point and the workpiece to the robot.
December 27, 2019
Date of Patent:
September 6, 2022
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE