Patents by Inventor Ying Lin

Ying Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240198632
    Abstract: A display device includes a protection assembly and an outer frame. The protection assembly includes a cover plate and an elastic structure. The elastic structure includes a first adhesive layer, a second adhesive layer, and an elastic layer. The first adhesive layer is adhered to the cover plate. The elastic layer is disposed between the first adhesive layer and the second adhesive layer. The outer frame is adhered to the second adhesive layer. A modulus of elasticity of the elastic structure is between 120 N/compression % and 200 N/compression %. A peel adhesive force between the second adhesive layer and the outer frame is between 8 N/25 mm and 100 N/25 mm.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Inventors: Shih Hao CHEN, Yun Chine LO, Yung Feng YEH, Tao LU, Shui Ying LIN
  • Publication number: 20240204065
    Abstract: A high frequency transistor includes a substrate, a plurality of gates, a plurality of sources/drains, a first metal layer, a plurality of source/drain contacts, and a plurality of first gate contacts. The gates extend along a first direction on a surface of the substrate, and the sources/drains are disposed in the substrate on both sides of each of the gates. The first metal layer has a first portion extending along the first direction and a second portion extending along a second direction, and the first direction is perpendicular to the second direction. The first portion is a discontinuous line segment having a discontinuous region in the second direction, and the second portion is a continuous line segment passing through the discontinuous region. The source/drain contacts are respectively connected to the first portion and the sources/drains. The first gate contacts are respectively connected to the second portion and the gates.
    Type: Application
    Filed: January 12, 2023
    Publication date: June 20, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hsin-Cheng Lin, Avishek Das, Kuan-Ying Chiu, Chee-Wee Liu
  • Patent number: 12015023
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20240195210
    Abstract: A soft start circuit of a UPS relay includes a three-phase pre-charging module, a first PFC module, a second PFC module, a relay module, a three-phase input voltage detection module, a bus voltage detection module and a relay control module. The relay control module is electrically connected to the three-phase input voltage detection module and the bus voltage detection module and controls the connection of the relay module, to control part of relays in the relay module to be turned on based on the A-phase input voltage, the B-phase input voltage, the C-phase input voltage and the bus voltage to soft start the relay. The relay can be safely turned on without being damaged by an impact current in a case that an input voltage is unbalanced.
    Type: Application
    Filed: October 16, 2023
    Publication date: June 13, 2024
    Applicant: Vertiv Corporation
    Inventors: Shaoqiang LIN, Wei XU, Xiaolu GUO, Ying WANG
  • Publication number: 20240196601
    Abstract: A memory structure and a method of manufacturing the same are provided. The method includes forming a gate structure and a source/drain region in a substrate, in which the source/drain region is next to the gate structure. A dry etching process is performed to form a trench in the source/drain region. A wet etching process is performed to expand the trench to form an expanded trench, in which the expanded trench has a polygonal cross section profile. A bit line contact is formed in the expanded trench.
    Type: Application
    Filed: February 19, 2024
    Publication date: June 13, 2024
    Inventor: Yu-Ying LIN
  • Publication number: 20240196764
    Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.
    Type: Application
    Filed: February 22, 2024
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Bo-Jiun Lin, Shao-Ming Yu, Yu-Chao Lin
  • Publication number: 20240194839
    Abstract: A micro light-emitting diode display is based on a conventional micro light-emitting diode display and includes at least one electrically conductive material layer or at least one functional material added to an encapsulation layer, so as to achieve antistatic effect. The micro light-emitting diode display solves the problem that the conventional micro light-emitting diode display is easily damaged by electrostatic breakdown.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 13, 2024
    Inventors: CHIA-MING FAN, WEN-YOU LAI, HSIEN-YING CHOU, PO-LUN CHEN, CHUN-TA CHEN, PO-CHING LIN
  • Patent number: 12009323
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The semiconductor structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first oxide layer formed below the a first substrate, a first bonding layer formed below the first oxide layer, and a first bonding via formed through the first bonding layer and the first oxide layer. The second semiconductor device includes a second oxide layer formed over a second substrate, a second bonding layer formed over the second oxide layer, and a second bonding via formed through the second bonding layer and the second oxide layer. The semiconductor structure also includes a bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 12009824
    Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Hui-Zhong Zhuang, Chi-Lin Liu
  • Patent number: 12009341
    Abstract: An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: June 11, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Po-Kai Chiu, Sheng-Tsai Wu, Yu-Min Lin, Wen-Hung Liu, Ang-Ying Lin, Chang-Sheng Chen
  • Publication number: 20240184393
    Abstract: Disclosed are a method and an electronic device for dynamically adjusting sensitivity of a touchpad. System information of an electronic device is detected. A currently used window where a cursor stays is determined, a current use behavior of the currently used window is obtained, and a first touch sensitivity adjustment coefficient is accordingly determined. A window characteristic of the currently used window and a statistical characteristic of each window object in the currently used window are obtained, and a second touch sensitivity adjustment coefficient is determined based on the system information, the window characteristic of the currently used window, and the statistical characteristic of each window object. A specific touch sensitivity adjustment coefficient is determined based on the first and second touch sensitivity adjustment coefficients. Current touch sensitivity of the touchpad is adjusted to specific touch sensitivity based on the specific touch sensitivity adjustment coefficient.
    Type: Application
    Filed: June 1, 2023
    Publication date: June 6, 2024
    Applicant: Acer Incorporated
    Inventors: Sheng-Lin Chiu, An-Cheng Lee, En-Shin Chen, Ying-Shih Hung
  • Publication number: 20240186417
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate, and a first gate structure formed over the first nanostructures. The semiconductor device structure includes a second gate structure formed over the second nanostructures, and the second gate structure includes a gate dielectric layer, a first type work function layer and a filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and the first isolation layer includes a first sidewall surface, and the first sidewall surface is in direct contact with a first interface between the gate dielectric layer and the first type work function layer and a second interface between the work function layer and the filling layer.
    Type: Application
    Filed: February 15, 2024
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao LIN, Wei-Sheng YUN, Tung-Ying LEE
  • Publication number: 20240188344
    Abstract: A light-emitting substrate includes a base substrate, light-emitting device(s) and a first insulating layer. A light-emitting device includes a first electrode, a light-emitting functional layer and a second electrode that are sequentially stacked. The first electrode includes a second sub-electrode and a first sub-electrode. The second sub-electrode includes a first portion covered by the first sub-electrode and a second portion except for the first portion. The first insulating layer has a first opening and a second opening. A portion of a side face of the first sub-electrode located on the second sub-electrode is covered by the first insulating layer. A portion of the light-emitting functional layer located in the first opening is in contact with the first sub-electrode, and a portion of the light-emitting functional layer located in the second opening is in contact with the second portion in the second sub-electrode.
    Type: Application
    Filed: May 31, 2021
    Publication date: June 6, 2024
    Inventors: Ying HAN, Yicheng LIN, Guang YAN, Pan XU, Dongfang YANG, Xing ZHANG, Zhan GAO, Guoying WANG, Dacheng ZHANG
  • Publication number: 20240188350
    Abstract: A light-emitting substrate includes a base substrate, an auxiliary electrode line, at least one light-emitting device, and at least one light-detecting device(s). The auxiliary electrode line is disposed on the base substrate. The at least one light-emitting device is disposed above the base substrate, and a light-emitting device includes a first electrode, a light-emitting functional layer and a second electrode that are sequentially stacked in a direction moving away from the base substrate. The at least one light-detecting device is disposed above the base substrate, and a light-detecting device includes a third electrode and a fourth electrode. The auxiliary electrode line is coupled to the fourth electrode and the second electrode.
    Type: Application
    Filed: May 31, 2021
    Publication date: June 6, 2024
    Inventors: Ying HAN, Yicheng LIN, Guang YAN, Pan XU, Mingi CHU, Dongfang YANG
  • Patent number: 12002842
    Abstract: A light-emitting diode, includes a substrate; a semiconductor stack formed on the substrate; a first current blocking patterned structure and a second current blocking patterned structure formed on the semiconductor stack and separated from each other; and a plurality of electrodes formed on the semiconductor stack and electrically connected to the semiconductor stack; wherein the first current blocking patterned structure is overlapped with one of the plurality of electrodes and the second current blocking patterned structure is not overlapped with the plurality of electrodes.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: June 4, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Hsin Ying Wang, Tzung Shiun Yeh, Yu Ling Lin, Bo Jiun Hu
  • Patent number: 12004385
    Abstract: Provided is a display substrate including a substrate, and a light-emitting device and an optical compensation structure which are located on the substrate. The optical compensation structure includes a photoelectric sensor, a transistor and a capacitor, and the photoelectric sensor is electrically connected to the transistor and the capacitor respectively. The photoelectric sensor includes a first electrode, a photosensitive layer located on a side of the first electrode distal from the substrate, and a second electrode located on a side of the photosensitive layer distal from the substrate; the transistor includes a source electrode, a drain electrode, a gate electrode and an active layer; and the capacitor includes a first electrode plate and a second electrode plate located on a side of the first electrode plate distal from the substrate.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: June 4, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Ying Han, Yicheng Lin, Pan Xu, Xing Zhang, Zhan Gao, Guang Yan
  • Patent number: 12000455
    Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Chen Ho, Chih Ping Liao, Chien Ting Lin, Jie-Ying Yang, Wei-Ming Wang, Ker-Hsun Liao, Chi-Hsun Lin
  • Publication number: 20240179969
    Abstract: A display panel has a display region, a fan-out region located on a side of the display region, and a bonding region located on a side of the fan-out region away from the display region. The display panel includes a gate driving circuit disposed in the display region, a plurality of data lines and a plurality of control signal lines that all extends from the display region to the fan-out region, and a plurality of data fan-out leads and a plurality of first fan-out leads that are all disposed in the fan-out region. Each data line is electrically connected to a data fan-out lead. The data fan-out leads are gathered to the bonding region. The control signal lines are electrically connected to the gate driving circuit. Each control signal line is electrically connected to a first fan-out lead. The first fan-out leads are gathered to the bonding region.
    Type: Application
    Filed: June 22, 2021
    Publication date: May 30, 2024
    Inventors: Ying HAN, Yicheng LIN, Pan XU, Guoying WANG, Xing ZHANG, Zhan GAO, Mingi CHU
  • Patent number: 11997933
    Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Yu Chao Lin
  • Patent number: 11996368
    Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.
    Type: Grant
    Filed: June 23, 2023
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Ying Huang, Yung-Ching Chen, Yueh-Chiou Lin, Yian-Liang Kuo