Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.

Abstract: A manufacturing method of an electronic device includes: providing a first substrate, which has a base layer and a plurality of electronic components disposed on the base layer; adhering adhesive material to each of the plurality of electronic components; providing a target substrate, wherein the target substrate and the first substrate are separated from each other by a distance; and transferring at least part of the plurality of electronic components adhered with the adhesive material to the target substrate through a laser process, wherein at least part of the plurality of electronic components are attached to the target substrate via the adhesive material.

Abstract: A smart digital computer platform is disclosed that collects, analyzes, and/or renders appropriate information about fugitive emissions identified by a sensor network-based emissions monitoring system in a facility. More specifically to the methods used by the smart digital computer platform to analyze, filter, and transform the collected monitoring data into a visual output that is capable of being rendered on a graphical user interface (GUI) on a screen display with, in some embodiments, a restricted form factor. For example, smart analytics may be used to cull, filter, and transform the data displayed in a pop-up dialog box on a GUI. In another example, the transformed data may be translated into a visual, graphical element that conveys an abundance of appropriate, tailored information to a particular type of user viewing the GUI.

Abstract: A package structure includes a carrier, a frame, and at least one photonic device. The carrier includes a substrate and a plurality of first metal pads and second metal pads. The substrate includes a first surface and a second surface that are opposite to each other. The first metal pads are disposed on the first surface. The second metal pads are disposed on the second surface. A thickness of each of the second metal pads is greater than that of each of the first metal pads. The frame is disposed on the carrier, and an accommodating space is formed between the frame and the carrier. The at least one photonic device is disposed in the accommodating space.

Abstract: An electronic apparatus including a touch display panel and a driver circuit is provided. The touch display panel includes a plurality of first electrodes and at least one second electrode. The plurality of first electrodes are arranged in an active area of the touch display panel, and the at least one second electrode is arranged in a border area of the touch display panel. The driver circuit is coupled to the touch display panel. The driver circuit is configured to drive the plurality of first electrodes to perform a touch sensing operation in a first period. The driver circuit is configured to drive the plurality of first electrodes and the at least one second electrode to perform a gesture sensing operation in a second period.

Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.

Abstract: The disclosure provides a test result recognizing method and a test result recognizing device. The method includes: controlling an image-capturing device to capture a first image of a display screen according to an image-capturing parameter; in response to determining that a reference image area including a first designated character string exists in the first image, controlling the image-capturing device to capture a first test image of the display screen according to the image-capturing parameter; extracting a first image area corresponding to the reference image area from the first test image, and performing a text dividing operation on the first image area to convert the first image area into a second image area; and performing a text recognition operation on the second image area to obtain a first test result corresponding to the first test image.

Abstract: To reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.

Abstract: A storage device for generating an identity code, includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores several first data having several bits. The second storage circuit stores several second data having several bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, and simultaneously reads the first data from the first storage circuit to form a second sequence. The reading circuit includes a processing circuit which simultaneously receives the first sequence and the second sequence, selects a first portion of the second sequence to form a target sequence according to the first sequence, and outputs the target sequence to serve as an identity code. Logical values of the bits of the first data and the second data are randomly distributed or pre-defined by a user.

Abstract: A reordering method performed by a receiving apparatus is provided. The receiving apparatus may receive a first PPDU from a transmitting apparatus, wherein the first PPDU includes a plurality of MPDUs, and the MPDUs correspond to the same BA window. The receiving apparatus may determine a traffic that each of the MPDUs belongs to according to an MPDU identification, wherein traffics that the plurality of MPDUs belonging to include a first traffic and a second traffic which is different from the first traffic. The receiving apparatus may perform a reordering operation for the MPDUs belonging to the first traffic, and a reordering operation for the MPDUs belonging to the second traffic, respectively. The receiving apparatus may transmit a BA frame in response to the first PPDU to the transmitting apparatus, wherein the BA frame includes information for indicating whether the MPDUs in the first PPDU have been successfully received.

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.

Abstract: The present disclosure provides a transferring head and a method for manufacturing an electronic device. The transferring head includes a substrate, a head unit, and a plurality of connecting elements. The head unit includes an electrode and a cantilever supporting the electrode. Two adjacent ones of the connecting elements are disposed between the substrate and the head unit. The electrode and a part of the cantilever are suspended over the substrate, and the cantilever is connected between one of the plurality of connecting elements and the electrode. The electrode is spaced apart from the plurality of connecting elements when viewed along a normal direction of the substrate.

Abstract: Dipole engineering techniques are disclosed that incorporate dipole dopant and/or nitrogen into gate dielectrics (e.g., high-k dielectric layers thereof) to realize multi-threshold voltage transistor tuning of transistors. The dipole engineering techniques include (1) forming a dipole dopant source layer over gate dielectrics of some transistors, but not other transistors, (2) forming a mask over gate dielectrics of some transistors, but not other transistors, (3) performing a nitrogen-containing thermal drive-in process, and (4) removing the dipole dopant source layer and the mask after the nitrogen-containing thermal drive-in process. The nitrogen-containing thermal drive-in process diffuses nitrogen and dipole dopant (n-dipole dopant and/or p-dipole dopant) into unmasked gate dielectrics having the dipole dopant source layer formed thereon, nitrogen into unmasked gate dielectrics, and dipole dopant into masked gate dielectrics having the dipole dopant source layer formed thereon.

Abstract: A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, a second nanostructure, a metal gate stack, and a spacer structure. The first nanostructure is between the second nanostructure and the substrate, the metal gate stack surrounds the first nanostructure and the second nanostructure, and the spacer structure surrounds an upper portion of the metal gate stack over the second nanostructure. The method includes removing the upper portion of the metal gate stack to form a first trench in the spacer structure. The method includes removing a first portion of the second nanostructure through the first trench after removing the upper portion of the metal gate stack.

Abstract: A touch apparatus includes a touch screen and a touch controller. The touch controller is configured to process touch sensing signals received from the touch screen to generate a touch coordinate with respect to a touch event occurring on the touch screen. The touch screen includes a plurality of first touch sensing electrodes and a plurality of second touch sensing electrodes. The first touch sensing electrodes are disposed in a center area of the touch screen, wherein at least one part of the first touch sensing electrodes are rectangular. The second touch sensing electrodes are disposed in an edge area of the touch screen surrounding the center area, wherein each of the second touch sensing electrodes is corresponding to a central angle and a plurality of central angles corresponding to the plurality of second touch sensing electrodes substantially equal.

Abstract: A tape laying device includes a tape transmission mechanism, a compaction head mechanism, a cutter mechanism, a heating mechanism and a motion mechanism. The tape transmission mechanism is configured to transmit the pre-impregnated tape. The compaction head mechanism, connected with the tape transmission mechanism, is configured to depress and drive the pre-impregnated tape transmitted by the tape transmission mechanism to follow a moving path so as to adhere the pre-impregnated tape onto the mould surface. The cutter mechanism is configured to cut the pre-impregnated tape. The heating mechanism, disposed downstream to the cutter mechanism, is configured to heat the pre-impregnated tape. The motion mechanism is used to have the cutter mechanism having an active path to move toward the moving path while the cutter mechanism cuts the pre-impregnated tape.